2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – I DD Specifications and Conditions Table 17: I DD Measurement Conditions for I DD6, I DD6ET, and I DD8 IDD6: Self Refresh Current IDD6ET: Self Refresh Current Normal Temperature Range Extended Temperature Range IDD Test TC = 0°C to +85°C TC = 0°C to +95°C IDD8: Reset2 CKE LOW LOW Midlevel External clock Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel tCK N/A N/A N/A tRC N/A N/A N/A tRAS N/A N/A N/A tRCD N/A N/A N/A tRRD N/A N/A N/A tRC N/A N/A N/A CL N/A N/A N/A AL N/A N/A N/A CS# Midlevel Midlevel Midlevel Command inputs Midlevel Midlevel Midlevel Row/column addresses Midlevel Midlevel Midlevel Bank addresses Midlevel Midlevel Midlevel Data I/O Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Midlevel ODT1 Enabled, midlevel Enabled, midlevel Midlevel Burst length N/A N/A N/A Active banks N/A N/A None Idle banks N/A N/A All SRT Disabled (normal) Enabled (extended) N/A ASR Disabled Disabled N/A Notes: 1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel. 2. During a cold boot RESET (initialization), current reading is valid after power is stable and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current reading is valid after RESET has been LOW for 200ns + t RFC. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved.
Table 18: I DD7 Measurement Loop CK, CK# Toggling CKE Static HIGH Sub-Loop 0 Cycle Number Command CS# RAS# CAS# WE# ODT 0 ACT 0 0 1 1 0 0 0 0 0 0 0 – 1 RDA 0 1 0 1 0 0 0 1 0 0 0 00000000 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 Repeat cycle 2 until nRRD - 1 nRRD ACT 0 0 1 1 0 1 0 0 0 F 0 – 1 nRRD + 1 nRRD + 2 RDA D 0 1 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 F F 0 0 00110011 – nRRD + 3 Repeat cycle nRRD + 2 until 2 × nRRD - 1 2 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 2 3 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 3 4 4 × nRRD 4 × nRRD + 1 D 1 0 0 0 0 3 0 0 0 F 0 Repeat cycle 4 × nRRD until nFAW - 1, if needed – 5 nFAW Repeat sub-loop 0, use BA[2:0] = 4 6 nFAW + nRRD Repeat sub-loop 1, use BA[2:0] = 5 7 nFAW + 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 6 8 nFAW + 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 7 9 10 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – I DD Specifications and Conditions nFAW + 4 × nRRD D 1 0 0 0 0 7 0 0 0 F 0 – nFAW + 4 × nRRD + 1 Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed 2 × nFAW ACT 0 0 1 1 0 0 0 0 0 F 0 – 2 × nFAW + 1 RDA 0 1 0 1 0 0 0 1 0 F 0 00110011 2 × nFAW + 2 D 1 0 0 0 0 0 0 0 0 F 0 – 2 × nFAW + 3 Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1 2 × nFAW + nRRD ACT 0 0 1 1 0 1 0 0 0 0 0 – 11 2 × nFAW + nRRD + 1 2 × nFAW + nRRD + 2 RDA D 0 1 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 00000000 – 2 × nFAW + nRRD + 3 Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1 12 2 × nFAW + 2 × nRRD Repeat sub-loop 10, use BA[2:0] = 2 13 2 × nFAW + 3 × nRRD Repeat sub-loop 11, use BA[2:0] = 3 14 2 × nFAW + 4 × nRRD 2 × nFAW + 4 × nRRD + 1 D 1 0 0 0 0 3 0 0 0 0 0 – Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed 15 3 × nFAW Repeat sub-loop 10, use BA[2:0] = 4 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. � 2006 Micron Technology, Inc. All rights reserved. BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data 3
Page 1 and 2: DDR3 SDRAM MT41J512M4 - 64 Meg x 4
Page 3 and 4: 2Gb: x4, x8, x16 DDR3 SDRAM Feature
Page 11 and 12: State Diagram Figure 2: Simplified
Page 13 and 14: 2Gb: x4, x8, x16 DDR3 SDRAM Functio
Page 15 and 16: Figure 4: 256 Meg x 8 Functional Bl
Page 17 and 18: Figure 7: 96-Ball FBGA - x16 (Top V
Page 19 and 20: Table 3: 78-Ball FBGA - x4, x8 Ball
Page 21 and 22: Table 4: 96-Ball FBGA - x16 Ball De
Page 23 and 24: Figure 9: 78-Ball FBGA - x4, x8 (HX
Page 25 and 26: Figure 11: 96-Ball FBGA - x16 (JT)
Page 27 and 28: Input/Output Capacitance Table 6: D
Page 29 and 30: Figure 12: Thermal Measurement Poin
Page 31 and 32: Table 9: I DD0 Measurement Loop CK,
Page 33 and 34: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
Page 35 and 36: Table 14: I DD4R Measurement Loop C
Page 37: Table 16: I DD5B Measurement Loop C
Page 41 and 42: Electrical Characteristics - I DD S
Page 43 and 44: Table 21: I DD Maximum Limits - Die
Page 45 and 46: Electrical Specifications - DC and
Page 47 and 48: Figure 13: Input Signal 0.925V 0.85
Page 49 and 50: Table 28: Differential Input Operat
Page 51 and 52: Figure 18: Definition of Differenti
Page 53 and 54: Figure 19: Nominal Slew Rate Defini
Page 55 and 56: ODT Characteristics Figure 21: ODT
Page 57 and 58: Table 33: R TT Effective Impedances
Page 59 and 60: Figure 23: t AON and t AOF Definiti
Page 61 and 62: Output Driver Impedance Figure 26:
Page 63 and 64: 34 Ohm Driver The 34� driver’s
Page 65 and 66: Alternative 40 Ohm Driver Table 45:
Page 67 and 68: Output Characteristics and Operatin
Page 69 and 70: Figure 28: Differential Output Sign
Page 71 and 72: Slew Rate Definitions for Different
Page 73 and 74: Table 53: DDR3-1333 Speed Bins DDR3
Page 75 and 76: Table 55: DDR3-1866 Speed Bins DDR3
Page 77 and 78: PDF: 09005aef826aaadc Micron Techno
Page 85 and 86: 2Gb: x4, x8, x16 DDR3 SDRAM Electri
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PDF: 09005aef826aaadc Micron Techno
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2Gb: x4, x8, x16 DDR3 SDRAM Electri
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Table 62: Derating Values for t IS/
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Figure 32: Nominal Slew Rate and t
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Figure 34: Tangent Line for t IS (C
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Data Setup, Hold, and Derating 2Gb:
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Table 68: Derating Values for t DS/
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2Gb: x4, x8, x16 DDR3 SDRAM Data Se
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Figure 37: Nominal Slew Rate for t
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Figure 39: Tangent Line for t DH (D
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2Gb: x4, x8, x16 DDR3 SDRAM Command
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Commands DESELECT NO OPERATION ZQ C
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PRECHARGE REFRESH 2Gb: x4, x8, x16
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DLL Disable Mode • All other self
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Figure 42: DLL Disable Mode to DLL
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Input Clock Frequency Change 2Gb: x
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Write Leveling Figure 45: Write Lev
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Write Leveling Procedure 2Gb: x4, x
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Write Leveling Mode Exit Procedure
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Figure 48: Initialization Sequence
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Figure 50: MRS to nonMRS Command Ti
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Table 77: Burst Order Burst Length
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Mode Register 1 (MR1) Figure 53: Mo
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On-Die Termination (ODT) WRITE LEVE
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Mode Register 2 (MR2) Figure 55: Mo
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SRT versus ASR 2Gb: x4, x8, x16 DDR
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Figure 58: MPR Block Diagram Memory
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MPR Read Predefined Pattern The pre
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ACTIVATE Operation Before any READ
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READ Operation Figure 66: READ Late
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2Gb: x4, x8, x16 DDR3 SDRAM READ Op
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Figure 77: Data Strobe Timing - REA
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Figure 80: t RPST Timing CK CK# DQS
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Figure 81: t WPRE Timing Figure 82:
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Figure 90: WRITE (BL8) to PRECHARGE
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Figure 93: Data Input Timing DQS, D
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Figure 94: Self Refresh Entry/Exit
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Power-Down Mode Power-down is synch
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Figure 95: Active Power-Down Entry
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Figure 98: Power-Down Entry After R
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Figure 102: ACTIVATE to Power-Down
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RESET Operation 2Gb: x4, x8, x16 DD
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On-Die Termination (ODT) Figure 107
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Dynamic ODT Dynamic ODT Special Use
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Table 89: Mode Registers for R TT(W
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Synchronous ODT Mode ODT Latency an
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2Gb: x4, x8, x16 DDR3 SDRAM - Micron

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