CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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4.5 Analyzing Transistor Circuits 104 unclear what feedback topology (e.g., shunt-series) is applicable, and how the circuit can be partitioned into a forward amplifier and feedback network. It turns out that this circuit actually employs unconditionally stable positive feedback — a situ- ation that is normally not considered in topology-based feedback analysis. Solving using DPI/SFG Analysis The SFG for the small-signal circuit in Figure 4.28 is given in Figure 4.29a. We see immediately that there are two feedback loops in this circuit. Loop L 1 is the feedback provided by the transconductance associated with transistor M1 . Since the loop gain of L1 is gm1( r || ds1 rds2) » 1 , the transmittance from iscx to vx is roughly 1 ⁄ gm1 . Thus, feedback causes node x to appear as a low impedance node even though its driving-point impedance of r || ds1 rds2 is quite high. i scx i scx – gm1 L 1 r || ds1 rds2 r || ds1 r || ds2 1 ⁄ gm1 g ds1 g ds1 Figure 4.29 SFG for determining output resistance of cascode current mirror a) complete graph, b) graph showing only main feedback loop. In order to help us analyze loop L 2 , we can collapse loop L 1 using the Source r ds1 Absorption Theorem as shown in Figure 4.29b. The loop gain of L 2 is v x a) b) i out i out gm1+ gds1 vx gm1+ gds1 L 2 r ds1 v out v out
4.5 Analyzing Transistor Circuits 105 Equation (4.21) shows that is positive and that we have a positive feedback loop. Stability is guaranteed because the loop gain is less than one; however, the value will be close to one since gds2 ⁄ gm1 ≈ 0 . The output impedance is given by the closed-loop expression (4.22) As expected, we obtain the same expression as Equation (4.20). We can now see that the output impedance will be enhanced because rds1 is divided by ( 1 – L2) which is near zero. In the process of obtaining the answer, we have gained a deeper understanding of the circuit using DPI/SFG analysis compared with using nodal analysis. 4.6 SUMMARY gm1+ gds1 L2 = ( r || ds1 r || ds2 1 ⁄ gm1) ( gm1+ gds1) × rds1 × gds1 = --------------------------------------------gds1 + gds2 + gm1 (4.21) R out ≡ v out -------- i out r ds1 In this chapter, we brought together the essential elements of the DPI/SFG analysis method. We advanced the current understanding of DPI/SFG analysis with the following contributions: g ds2 g ds2 = 1 – --------------------------------------------- ≈ 1 – --------- < 1 gds1 + gds2 + gm1 gm1 L 2 A rds1 gds1 + gds2 + gm1 = ----------------- = --------------- = rds1 × --------------------------------------------- 1 – Aβ 1 – L2 gds2 gds1 + gds2 + gm1 = × --------------------------------------------- = rds1 + rds2 + gm1r ds1rds2 g ds2 ≈ ( 1 + gm1r ds2)rds1 • We developed a general formulation of the method, first by justifying driving-point impedance analysis as a cause-and-effect interpretation of Kirchhoff’s Current Law, and then by applying signal-flow graph theory. • We extended the DPI/SFG analysis procedure to handle circuits with floating voltage sources. • We used the method to derive Blackman’s Impedance Formula. • We derived the small-signal signal-flow graphs of both bipolar and MOS transistors.
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CMOS Optical Preamplifier Design Us
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To achieve low-voltage operation, w
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Table of Contents CHAPTER 1 INTRODU
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CHAPTER 1 1.1 OVERVIEW Introduction
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Information Source Modulator Drive
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1.2 Thesis Outline 5 [Ohhata,1999].
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1.2 Thesis Outline 7 technique call
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1.2 Thesis Outline 9 Detector in St
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E e + - V bias 2.1 Photodetectors 1
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Diode Capacitance (pF) Diode capaci
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2.2 Optical Preamplifier Structures
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2.3 Transimpedance Amplifier Design
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I dc 2.3 Transimpedance Amplifier D
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Source Figure 2.11 General structur
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A = = For = 1V , the solution is v
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The gain of the forward amplifier c
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Feedback Analysis Using Return Rati
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2.4 Circuit Analysis Techniques 33
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2.5 An Overview of Signal-Flow Grap
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1 x1 x2 2.5 An Overview of Signal-F
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2.6 SUMMARY REFERENCES • ∆ k =
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Symp. Circuits Systems, vol. 3, pp.
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CHAPTER 3 New Transimpedance Amplif
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3.1 A Differential Transimpedance A
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3.2 A Feedback Topology for Ambient
Page 59 and 60: 3.2 A Feedback Topology for Ambient
Page 61 and 62: Transimpedance (dBΩ) 90 80 60 40
Page 63 and 64: 3.3 A Low-Voltage Transimpedance Am
Page 73 and 74: C 3 Φ1VB M 3 V B- =0.7V M 7 Figure
Page 77 and 78: 3.4 SUMMARY 3.4 Summary 71 In this
Page 79 and 80: 3.4 Summary 73 Y. Nakagome et al.,
Page 81 and 82: 4.1 Introduction 75 back topology o
Page 83 and 84: 4.2 Circuit Analysis Using Driving-
Page 91 and 92: 4.3 DPI/SFG: Combining DPI Analysis
Page 93 and 94: 4.4 Determining Port Impedances 87
Page 95 and 96: v i R in v o R out 4.4 Determining
Page 97 and 98: id » ro and 1 ⁄ rid « Av ⁄ ro
Page 103 and 104: Z b r e g m 4.5 Analyzing Transisto
Page 105 and 106: 4.5 Analyzing Transistor Circuits 9
Page 107 and 108: Figure 4.25 SFG for the source foll
Page 109: 4.5 Analyzing Transistor Circuits 1
Page 113 and 114: 4.5 Analyzing Transistor Circuits 1
Page 115 and 116: 5.1 Analysis of the Low-Voltage Tra
Page 117 and 118: 5.1 Analysis of the Low-Voltage Tra
Page 119 and 120: 5.2 DEVELOPING AN ANALYTIC CIRCUIT
Page 121 and 122: Z in 5.2 Developing an Analytic Cir
Page 123 and 124: 5.2 Developing an Analytic Circuit
Page 125 and 126: I n1 : i in I n2 -I n1 i scin ( sCi
Page 129 and 130: I nRf : 5.2 Developing an Analytic
Page 131 and 132: DC transimpedance gain: Pole locati
Page 133 and 134: Frequency (MHz) 500 450 400 350 300
Page 135 and 136: Pole frequencies(MHz) 500 450 400 3
Page 137 and 138: Optimizing Sensitivity 5.2 Developi
Page 141 and 142: Transimpedance Volts dB (lin) Gain
Page 143 and 144: CHAPTER 6 Implementation and Experi
Page 145 and 146: 6.1 A 1V Optical Receiver Front-End
Page 149 and 150: 6.1.2 Experimental Results 6.1 A 1V
Page 151 and 152: Gain(dB) 0 −1 −2 −3 −4 −5
Page 159 and 160: Clock signal of voltage doubler Eye
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6.2 Variable-Gain Transimpedance Am
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6.2.2 Experimental Results 6.2 Vari
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6.3 Summary and State-of-the-Art Co
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Reference Outputs Technology Supply
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CHAPTER 7 Conclusions 7.1 SUMMARY A
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7.2 Future Work 165 The significanc
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7.2 Future Work 167 supply and subs
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v s i ti that part of the SFG for Q
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Thus, P1 ′ = b = 500Ω ∆1 ′
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itive representation of circuit dyn
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Bipolar Transistor i scb Z b v b b
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CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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