CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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6.1 A 1V <strong>Optical</strong> Receiver Front-End 142 Figure 6.6 shows the differential output buffer that is designed to drive 50Ω loads. Transistor is very wide in order to decrease its saturation voltage so that the input common-mode range of the buffer is maximized. In contrast, transistors M 1 and are biased with a very high saturation voltage in order to maximize the M 2 bandwidth and the input linear range which is about 400mV (differential). The tail current is nominally 15 mA, and is controlled through a current mirror biased using an external resistor. Input Test Transconductor The input test transconductor, shown in Figure 6.7, allows us to generate test currents on-chip. The transconductor has an linear input range of about 200mV (differential). The tail current is nominally 30µA, but is adjustable through an external bias resistor M 3 v in+ 50Ω 50Ω Vbias Out- M 1 3V Out+ M 3 M 2 15 mA v in- M1,2 = 100/0.4 M3 =1000/0.6 Figure 6.6 Output buffer shown with external 50 Ω resistors.
6.1.2 Experimental Results 6.1 A 1V <strong>Optical</strong> Receiver Front-End 143 A micrograph of the fabricated test chip is shown in Figure 6.8. The chip measures 1.0mm × 1.6mm and occupies an active area of 0.13mm . The main signal 2 path runs through the centre of the chip, from left to right. The bias voltage doubler was placed in the far lower corner, away from the output buffer and output driver to minimize noise coupled through parasitics. The power consumption of the 1V front-end circuit is 1mW. The power consumption of the 3V test circuitry is 45mW, and is essentially due to the output buffer. An external 1pF capacitor was used to model the photodiode during electri- cal testing, while a Mitel 1A354 PIN photodiode was used to construct the actual optical link. The typical capacitance of the photodiode is 1pF for a bias voltage of 1V or more. Frequency Response Measurements In- Vbias M5 3 V M1 M2 30 uA M3 M4 In+ Iout M1,2 = 5/0.8 M3,4 = 10/0.6 M5 = 20/0.8 Figure 6.7 Input test transconductor circuit. The measured frequency response of the output buffer with source follower is shown in Figure 6.9. The buffer has a loss of 4dB at the midband frequency of 20MHz, and its gain remains within +0.5dB and -3dB from 1MHz to 100MHz. The remaining frequency responses presented for this chip take into account the
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CMOS Optical Preamplifier Design Us
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To achieve low-voltage operation, w
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Table of Contents CHAPTER 1 INTRODU
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CHAPTER 1 1.1 OVERVIEW Introduction
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Information Source Modulator Drive
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1.2 Thesis Outline 5 [Ohhata,1999].
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1.2 Thesis Outline 7 technique call
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1.2 Thesis Outline 9 Detector in St
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E e + - V bias 2.1 Photodetectors 1
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Diode Capacitance (pF) Diode capaci
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2.2 Optical Preamplifier Structures
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2.3 Transimpedance Amplifier Design
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I dc 2.3 Transimpedance Amplifier D
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Source Figure 2.11 General structur
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A = = For = 1V , the solution is v
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The gain of the forward amplifier c
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Feedback Analysis Using Return Rati
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2.4 Circuit Analysis Techniques 33
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2.5 An Overview of Signal-Flow Grap
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1 x1 x2 2.5 An Overview of Signal-F
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2.6 SUMMARY REFERENCES • ∆ k =
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Symp. Circuits Systems, vol. 3, pp.
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CHAPTER 3 New Transimpedance Amplif
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3.1 A Differential Transimpedance A
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3.2 A Feedback Topology for Ambient
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3.2 A Feedback Topology for Ambient
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Transimpedance (dBΩ) 90 80 60 40
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3.3 A Low-Voltage Transimpedance Am
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C 3 Φ1VB M 3 V B- =0.7V M 7 Figure
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3.4 SUMMARY 3.4 Summary 71 In this
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3.4 Summary 73 Y. Nakagome et al.,
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4.1 Introduction 75 back topology o
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4.2 Circuit Analysis Using Driving-
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4.3 DPI/SFG: Combining DPI Analysis
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4.4 Determining Port Impedances 87
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v i R in v o R out 4.4 Determining
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Page 99 and 100: 4.4 Determining Port Impedances 93
Page 101 and 102: 4.4 Determining Port Impedances 95
Page 103 and 104: Z b r e g m 4.5 Analyzing Transisto
Page 105 and 106: 4.5 Analyzing Transistor Circuits 9
Page 107 and 108: Figure 4.25 SFG for the source foll
Page 115 and 116: 5.1 Analysis of the Low-Voltage Tra
Page 117 and 118: 5.1 Analysis of the Low-Voltage Tra
Page 119 and 120: 5.2 DEVELOPING AN ANALYTIC CIRCUIT
Page 121 and 122: Z in 5.2 Developing an Analytic Cir
Page 123 and 124: 5.2 Developing an Analytic Circuit
Page 125 and 126: I n1 : i in I n2 -I n1 i scin ( sCi
Page 129 and 130: I nRf : 5.2 Developing an Analytic
Page 131 and 132: DC transimpedance gain: Pole locati
Page 133 and 134: Frequency (MHz) 500 450 400 350 300
Page 135 and 136: Pole frequencies(MHz) 500 450 400 3
Page 137 and 138: Optimizing Sensitivity 5.2 Developi
Page 141 and 142: Transimpedance Volts dB (lin) Gain
Page 143 and 144: CHAPTER 6 Implementation and Experi
Page 145 and 146: 6.1 A 1V Optical Receiver Front-End
Page 147: 6.1 A 1V Optical Receiver Front-End
Page 151 and 152: Gain(dB) 0 −1 −2 −3 −4 −5
Page 159 and 160: Clock signal of voltage doubler Eye
Page 161 and 162: 6.2 Variable-Gain Transimpedance Am
Page 163 and 164: 6.2.2 Experimental Results 6.2 Vari
Page 165 and 166: 6.3 Summary and State-of-the-Art Co
Page 167 and 168: Reference Outputs Technology Supply
Page 169 and 170: CHAPTER 7 Conclusions 7.1 SUMMARY A
Page 171 and 172: 7.2 Future Work 165 The significanc
Page 173 and 174: 7.2 Future Work 167 supply and subs
Page 175 and 176: v s i ti that part of the SFG for Q
Page 177 and 178: Thus, P1 ′ = b = 500Ω ∆1 ′
Page 179 and 180: itive representation of circuit dyn
Page 181 and 182: Bipolar Transistor i scb Z b v b b
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CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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