CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

3.3 A Low-Voltage Transimpedance Amplifier 69
The bias voltage doubler requires non-overlapping clock signals to clearly
define the two phases of the circuit’s operation. A non-overlapping clock generator
based on [Martin,1981] was incorporated into the doubler circuit and is shown in
Figure 3.25.
Figure 3.25 Non-overlapping clock generator.
To illustrate the expanded range of the proposed bias voltage doubler over that
of the basic charge pump cell shown in Figure 3.19, we ran two simulations of the
two circuits at start up. For the basic charge pump, the supply voltage was equal to
the desired bias voltage. A small output load capacitance of 0.5 pF was chosen to
speed up the transient response. The first simulation used an input voltage of 0.85V
and is shown in Figure 3.26. We see that both circuits come to within 20mV of the
ideal level. The slight undershoot is a result of parasitic capacitance on the top
plates of the level-shifting capacitors. This undershoot can be easily compensated
for by increasing the input bias voltage. The response of the proposed doubler is
faster due to the reduced switch resistance afforded by the dedicated charge pump
driving the output switches. In the second simulation, the input bias voltage is
reduced to 0.75V. As shown in Figure 3.27, only the proposed doubler circuit man-
ages to reach the desired level in this case. With the basic charge pump, the 0.75V
supply provides a reduced clock swing that is barely enough to initially turn on
M 1
External clock
switches and , and the switches quickly become ineffective as the threshold
M 2
voltages of switches and increase due to the body effect.
M 1
M 2
Φ 1
Φ 2