CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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Constant- Bias Circuit 6.1 A 1V Optical Receiver Front-End 140 The 1V bias circuit used in the receiver is shown in Figure 6.4. The circuit is commonly referred to as a constant- bias circuit because it is designed to stabi- lized the transconductances of the transistors relative to the external resistor, [Steininger,1990]. The design is adopted from [Johns,1997], but the cascode devices associated with transistors and have been removed so that the drain-to- source voltages of transistors and are better matched to those of transistors M 1 g m and respectively. The start-up circuit shown on the right is required to pre- M 4 Vbp Vin vent the circuit from remaining in an alternate stable state in which all the device currents are zero. 1V 3V Analog Multiplexor and Output Buffer M2 M1 M3 Limiter The analog multiplexor (MUX) and output buffer together provide the crucial facility to observe high-speed signals along the signal path. The analog multiplexor connects four possible signals to the output buffer: a direct external input for charac- terizing the output buffer, the preamplifier output, the first post amplifier output, and the second post amplifier output. The multiplexor is made up of four source follower buffers that are all connected to the signal terminal of the output buffer while the other buffer input terminal is connected to an external bias voltage. The source 50Ω RX Mout Output driver M1 = 1x10/0.4 M2 = 1x20/0.4 Mn = 1x5/1 Mout =100/0.4 Figure 6.3 Final limiter stage. Transistor sizes as shown. M 2 M 2 g m M 3 M 3 R bias
6.1 A 1V Optical Receiver Front-End 141 followers have an enable control as shown in Figure 6.5; when disabled, all bias currents are turned off, and the gate of is cut off from the input signal for improved M 1 isolation. Two external pins control a digital 4x1 decoder that is used to select the desired source follower while disabling the others. M1 M5 M3 Rbias M2 M4 16 uA M6 M9 M10 16 uA M8 M7 Vbp Vbpc Vbnc Vbn M1 = 1x40/0.6 M2 = 4x40/0.6 M3,4 = 1x10/0.6 M5 = 2x40/0.4 M6 = 2x10/0.4 M7 = 1x10/0.6 M8 = 1x10/1.0 M9 = 1x20/0.6 M10 = 1x3/5 Rbias = 5.5kOhms Figure 6.4 1V Constant-g m bias circuit with start-up circuitry. Transistor sizes as shown. M 3 I bias Enable v in sw 1 sw 3 3 V sw 2 M 2 M 1 v out Vbp Vbpc Vbnc Start-up circuitry M1 = 8/0.6 M2,3 = 48/0.8 sw1 = 2/0.4 sw2,3 = 4/0.4 Figure 6.5 Source follower with enable control.
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CMOS Optical Preamplifier Design Us
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To achieve low-voltage operation, w
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Table of Contents CHAPTER 1 INTRODU
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CHAPTER 1 1.1 OVERVIEW Introduction
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Information Source Modulator Drive
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1.2 Thesis Outline 5 [Ohhata,1999].
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1.2 Thesis Outline 7 technique call
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1.2 Thesis Outline 9 Detector in St
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E e + - V bias 2.1 Photodetectors 1
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Diode Capacitance (pF) Diode capaci
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2.2 Optical Preamplifier Structures
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2.3 Transimpedance Amplifier Design
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I dc 2.3 Transimpedance Amplifier D
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Source Figure 2.11 General structur
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A = = For = 1V , the solution is v
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The gain of the forward amplifier c
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Feedback Analysis Using Return Rati
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2.4 Circuit Analysis Techniques 33
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2.5 An Overview of Signal-Flow Grap
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1 x1 x2 2.5 An Overview of Signal-F
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2.6 SUMMARY REFERENCES • ∆ k =
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Symp. Circuits Systems, vol. 3, pp.
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CHAPTER 3 New Transimpedance Amplif
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3.1 A Differential Transimpedance A
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3.2 A Feedback Topology for Ambient
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3.2 A Feedback Topology for Ambient
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Transimpedance (dBΩ) 90 80 60 40
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3.3 A Low-Voltage Transimpedance Am
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C 3 Φ1VB M 3 V B- =0.7V M 7 Figure
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3.4 SUMMARY 3.4 Summary 71 In this
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3.4 Summary 73 Y. Nakagome et al.,
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4.1 Introduction 75 back topology o
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4.2 Circuit Analysis Using Driving-
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4.3 DPI/SFG: Combining DPI Analysis
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4.4 Determining Port Impedances 87
Page 95 and 96: v i R in v o R out 4.4 Determining
Page 97 and 98: id » ro and 1 ⁄ rid « Av ⁄ ro
Page 99 and 100: 4.4 Determining Port Impedances 93
Page 101 and 102: 4.4 Determining Port Impedances 95
Page 103 and 104: Z b r e g m 4.5 Analyzing Transisto
Page 105 and 106: 4.5 Analyzing Transistor Circuits 9
Page 107 and 108: Figure 4.25 SFG for the source foll
Page 115 and 116: 5.1 Analysis of the Low-Voltage Tra
Page 117 and 118: 5.1 Analysis of the Low-Voltage Tra
Page 119 and 120: 5.2 DEVELOPING AN ANALYTIC CIRCUIT
Page 121 and 122: Z in 5.2 Developing an Analytic Cir
Page 123 and 124: 5.2 Developing an Analytic Circuit
Page 125 and 126: I n1 : i in I n2 -I n1 i scin ( sCi
Page 129 and 130: I nRf : 5.2 Developing an Analytic
Page 131 and 132: DC transimpedance gain: Pole locati
Page 133 and 134: Frequency (MHz) 500 450 400 350 300
Page 135 and 136: Pole frequencies(MHz) 500 450 400 3
Page 137 and 138: Optimizing Sensitivity 5.2 Developi
Page 141 and 142: Transimpedance Volts dB (lin) Gain
Page 143 and 144: CHAPTER 6 Implementation and Experi
Page 145: 6.1 A 1V Optical Receiver Front-End
Page 149 and 150: 6.1.2 Experimental Results 6.1 A 1V
Page 151 and 152: Gain(dB) 0 −1 −2 −3 −4 −5
Page 153 and 154: 6.1 A 1V Optical Receiver Front-End
Page 159 and 160: Clock signal of voltage doubler Eye
Page 161 and 162: 6.2 Variable-Gain Transimpedance Am
Page 163 and 164: 6.2.2 Experimental Results 6.2 Vari
Page 165 and 166: 6.3 Summary and State-of-the-Art Co
Page 167 and 168: Reference Outputs Technology Supply
Page 169 and 170: CHAPTER 7 Conclusions 7.1 SUMMARY A
Page 171 and 172: 7.2 Future Work 165 The significanc
Page 173 and 174: 7.2 Future Work 167 supply and subs
Page 175 and 176: v s i ti that part of the SFG for Q
Page 177 and 178: Thus, P1 ′ = b = 500Ω ∆1 ′
Page 179 and 180: itive representation of circuit dyn
Page 181 and 182: Bipolar Transistor i scb Z b v b b
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CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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