CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

Rbias
Vin+
1V
10kHz
clock
Vin
Select
(2-bits)
Optical Front-End IC
Charge
Pump
Bias
Circuit
Preamp
Vin- Test
transconductor
Variable-Gain Post Amplifiers
7kΩ 3.3pF 7kΩ
3.3pF
Post Amp #1
6.1 A 1V Optical Receiver Front-End 138
3.3pF
Post Amp #2
analog
MUX
Figure 6.1 System-level block diagram of 1V optical receiver. Shaded blocks
indicate the use of a 3V supply.
In the optical receiver, additional gain stages are required after the optical
preamplifier to provide sufficient amplification for the final limiter stage. We can
take advantage of our existing work on transimpedance amplifiers by adopting a
transconductance-transimpedance topology [Cherry,1963], [Wang,1995]. A maxi-
mum gain of 40dB was achieved by cascading two stages, each with a variable gain
up to 20dB. A variable gain is realized by either varying the transconductance
[Gomez,1992] or the transimpedance. We chose the latter since our transimpedance
design provides a variable gain with a well controlled bandwidth.
Output
Buffer
Figure 6.2 shows a schematic of a single variable-gain amplifier. The input
transconductance stage is biased by the output level of the previous stage. The inter-
V DGB
Limiter
Output
driver
200pF
50Ω
Digital
output
50Ω
+
Out
-
50Ω