CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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v 2 4.3 DPI/SFG: Combining DPI <strong>Analysis</strong> and Signal-Flow Graphs 86 4 S 1 S 2 S Notice how the 2S conductance can be ignored as its terminals are shorted together. Short-circuit current i sc2 is determined by considering the effect of each source sep- arately. With a little practice, the following procedure can be done by inspection. For the sake of clarity, however, we illustrate the individual short-circuit compo- nents in Figure 4.8. Notice from the subcircuits of sources v 5 and v 6 , that any element connected across the source does not contribute to the short-circuit current as 8 S Figure 4.7 Simplified circuit for determining Z DP2 . the element and source form a loop around which current can circulate. 2A source: 2A 2 S 8 S 2A v6 source: 2S v5 source: 0 2v 6 v 6 Figure 4.8 Simplified circuits illustrating short-circuit contributions of four separate sources. 8v 5 v 1 source: v 1 2S v 5 10v 5 4 S 4v 1 2v 5 8S 8v 5
4.4 Determining Port Impedances 87 The final step involves re-establishing the constraints on the voltage sources, giving The resulting SFG is shown in Figure 4.9a. Node voltages v 3 and v 4 are left out in order to simplify the graph. These nodes are not part of the chosen voltage tree, and their values can be easily determined once the voltages of the tree are known. The SFG can be simplified to that in Figure 4.9b which conforms to the traditional feedback structure of Figure 2.19 found on page 37, and as such, we can use the equiva- lence relation to obtain the final equations: Notice from the SFG that, because of the zero transmittance, the value of v 6 has no affect on the voltage at node 2! Again, this is because any current v 6 generates cir- culates around through the 2S conductance resulting in no net current into node 2. Such observations help illustrate the way in which signal-flow graphs can provide us with insight into the operation of a circuit, revealing relations that are not imme- diately apparent from the circuit. 4.4 DETERMINING PORT IMPEDANCES v 1 = – 1V v2 = Z DP2I SC2 v3 = v2 + v5 v4 = v2 + v5 – v6 v5 = 3( v1 – v2) = 0.5V v 6 v2 = 1⁄ 13 ------------------------- × 22 1 – 24 ⁄ 13 = – 2V v5 = 3( v1 – v2) = 3V v3 = v2 + v5 = 1V v4 = v1 + v5 – v6 = 0.5V Once an SFG has been generated for a circuit, the port impedance at any node can be determined by inserting a test current source at the node of interest and determining the effect of its current on the node voltage. Although one can also apply a
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CMOS Optical Preamplifier Design Us
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To achieve low-voltage operation, w
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Table of Contents CHAPTER 1 INTRODU
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CHAPTER 1 1.1 OVERVIEW Introduction
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Information Source Modulator Drive
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1.2 Thesis Outline 5 [Ohhata,1999].
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1.2 Thesis Outline 7 technique call
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1.2 Thesis Outline 9 Detector in St
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E e + - V bias 2.1 Photodetectors 1
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Diode Capacitance (pF) Diode capaci
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2.2 Optical Preamplifier Structures
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2.3 Transimpedance Amplifier Design
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I dc 2.3 Transimpedance Amplifier D
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Source Figure 2.11 General structur
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A = = For = 1V , the solution is v
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The gain of the forward amplifier c
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Feedback Analysis Using Return Rati
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2.4 Circuit Analysis Techniques 33
Page 41 and 42: 2.5 An Overview of Signal-Flow Grap
Page 43 and 44: 1 x1 x2 2.5 An Overview of Signal-F
Page 45 and 46: 2.6 SUMMARY REFERENCES • ∆ k =
Page 47 and 48: Symp. Circuits Systems, vol. 3, pp.
Page 49 and 50: CHAPTER 3 New Transimpedance Amplif
Page 51 and 52: 3.1 A Differential Transimpedance A
Page 57 and 58: 3.2 A Feedback Topology for Ambient
Page 59 and 60: 3.2 A Feedback Topology for Ambient
Page 61 and 62: Transimpedance (dBΩ) 90 80 60 40
Page 63 and 64: 3.3 A Low-Voltage Transimpedance Am
Page 73 and 74: C 3 Φ1VB M 3 V B- =0.7V M 7 Figure
Page 77 and 78: 3.4 SUMMARY 3.4 Summary 71 In this
Page 79 and 80: 3.4 Summary 73 Y. Nakagome et al.,
Page 81 and 82: 4.1 Introduction 75 back topology o
Page 83 and 84: 4.2 Circuit Analysis Using Driving-
Page 91: 4.3 DPI/SFG: Combining DPI Analysis
Page 95 and 96: v i R in v o R out 4.4 Determining
Page 97 and 98: id » ro and 1 ⁄ rid « Av ⁄ ro
Page 99 and 100: 4.4 Determining Port Impedances 93
Page 101 and 102: 4.4 Determining Port Impedances 95
Page 103 and 104: Z b r e g m 4.5 Analyzing Transisto
Page 105 and 106: 4.5 Analyzing Transistor Circuits 9
Page 107 and 108: Figure 4.25 SFG for the source foll
Page 115 and 116: 5.1 Analysis of the Low-Voltage Tra
Page 117 and 118: 5.1 Analysis of the Low-Voltage Tra
Page 119 and 120: 5.2 DEVELOPING AN ANALYTIC CIRCUIT
Page 121 and 122: Z in 5.2 Developing an Analytic Cir
Page 123 and 124: 5.2 Developing an Analytic Circuit
Page 125 and 126: I n1 : i in I n2 -I n1 i scin ( sCi
Page 129 and 130: I nRf : 5.2 Developing an Analytic
Page 131 and 132: DC transimpedance gain: Pole locati
Page 133 and 134: Frequency (MHz) 500 450 400 350 300
Page 135 and 136: Pole frequencies(MHz) 500 450 400 3
Page 137 and 138: Optimizing Sensitivity 5.2 Developi
Page 141 and 142: Transimpedance Volts dB (lin) Gain
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CHAPTER 6 Implementation and Experi
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6.1 A 1V Optical Receiver Front-End
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6.1.2 Experimental Results 6.1 A 1V
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Gain(dB) 0 −1 −2 −3 −4 −5
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Clock signal of voltage doubler Eye
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6.2 Variable-Gain Transimpedance Am
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6.2.2 Experimental Results 6.2 Vari
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6.3 Summary and State-of-the-Art Co
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Reference Outputs Technology Supply
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CHAPTER 7 Conclusions 7.1 SUMMARY A
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7.2 Future Work 165 The significanc
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7.2 Future Work 167 supply and subs
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v s i ti that part of the SFG for Q
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Thus, P1 ′ = b = 500Ω ∆1 ′
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itive representation of circuit dyn
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Bipolar Transistor i scb Z b v b b
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CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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