CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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Rbias Vin+ 1V 10kHz clock Vin Select (2-bits) Optical Front-End IC Charge Pump Bias Circuit Preamp Vin- Test transconductor Variable-Gain Post Amplifiers 7kΩ 3.3pF 7kΩ 3.3pF Post Amp #1 6.1 A 1V Optical Receiver Front-End 138 3.3pF Post Amp #2 analog MUX Figure 6.1 System-level block diagram of 1V optical receiver. Shaded blocks indicate the use of a 3V supply. In the optical receiver, additional gain stages are required after the optical preamplifier to provide sufficient amplification for the final limiter stage. We can take advantage of our existing work on transimpedance amplifiers by adopting a transconductance-transimpedance topology [Cherry,1963], [Wang,1995]. A maxi- mum gain of 40dB was achieved by cascading two stages, each with a variable gain up to 20dB. A variable gain is realized by either varying the transconductance [Gomez,1992] or the transimpedance. We chose the latter since our transimpedance design provides a variable gain with a well controlled bandwidth. Output Buffer Figure 6.2 shows a schematic of a single variable-gain amplifier. The input transconductance stage is biased by the output level of the previous stage. The inter- V DGB Limiter Output driver 200pF 50Ω Digital output 50Ω + Out - 50Ω
6.1 A 1V Optical Receiver Front-End 139 mediate current is then converted back to a voltage by the transimpedance stage. The transimpedance stage uses a standard current mirror without cascode devices in order to maximize signal swing. Variable gain is achieved by adjusting the central gate bias voltage generated by the voltage doubler, . v bp v bc Limiting Amplifier and Digital Output Driver v in 160 uA 16 uA M 3 M 2 M M 1 4 V DGB The limiting amplifier is used to regenerate digital levels from an analog signal, and is shown in Figure 6.3. The circuit consists of a common-source input stage that is loaded by the diode-connected transistor . Transistor biases the output of the common-source stage around the threshold voltage of the inverters. The inverters provide enough additional gain to regenerate the digital logic levels. M 5 The output driver is used to drive the digital signal off-chip. It consists of a wide, open-drain NMOS device that is connected to an external 50Ω load. The nominal M 7 M 6 drive current is 4 mA which provides 200mV of output swing. 1V v DGB R f Transconductance Transimpedance 64 uA v out M1 = 10x10/0.6 M2 = 20x10/0.4 M3 = 20x20/0.6 M4 = 1x10/0.6 M5 = 1x40/0.6 M6 = 4x10/0.6 M7 = 4x40/0.6 Mrf = 1x4/1.3 Figure 6.2 Variable-gain post amplifier stage. Transistor sizes as shown. M 3 M 3
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CMOS Optical Preamplifier Design Us
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To achieve low-voltage operation, w
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Table of Contents CHAPTER 1 INTRODU
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CHAPTER 1 1.1 OVERVIEW Introduction
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Information Source Modulator Drive
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1.2 Thesis Outline 5 [Ohhata,1999].
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1.2 Thesis Outline 7 technique call
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1.2 Thesis Outline 9 Detector in St
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E e + - V bias 2.1 Photodetectors 1
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Diode Capacitance (pF) Diode capaci
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2.2 Optical Preamplifier Structures
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2.3 Transimpedance Amplifier Design
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I dc 2.3 Transimpedance Amplifier D
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Source Figure 2.11 General structur
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A = = For = 1V , the solution is v
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The gain of the forward amplifier c
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Feedback Analysis Using Return Rati
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2.4 Circuit Analysis Techniques 33
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2.5 An Overview of Signal-Flow Grap
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1 x1 x2 2.5 An Overview of Signal-F
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2.6 SUMMARY REFERENCES • ∆ k =
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Symp. Circuits Systems, vol. 3, pp.
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CHAPTER 3 New Transimpedance Amplif
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3.1 A Differential Transimpedance A
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3.2 A Feedback Topology for Ambient
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3.2 A Feedback Topology for Ambient
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Transimpedance (dBΩ) 90 80 60 40
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3.3 A Low-Voltage Transimpedance Am
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C 3 Φ1VB M 3 V B- =0.7V M 7 Figure
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3.4 SUMMARY 3.4 Summary 71 In this
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3.4 Summary 73 Y. Nakagome et al.,
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4.1 Introduction 75 back topology o
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4.2 Circuit Analysis Using Driving-
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4.3 DPI/SFG: Combining DPI Analysis
Page 93 and 94: 4.4 Determining Port Impedances 87
Page 95 and 96: v i R in v o R out 4.4 Determining
Page 97 and 98: id » ro and 1 ⁄ rid « Av ⁄ ro
Page 103 and 104: Z b r e g m 4.5 Analyzing Transisto
Page 105 and 106: 4.5 Analyzing Transistor Circuits 9
Page 107 and 108: Figure 4.25 SFG for the source foll
Page 115 and 116: 5.1 Analysis of the Low-Voltage Tra
Page 117 and 118: 5.1 Analysis of the Low-Voltage Tra
Page 119 and 120: 5.2 DEVELOPING AN ANALYTIC CIRCUIT
Page 121 and 122: Z in 5.2 Developing an Analytic Cir
Page 123 and 124: 5.2 Developing an Analytic Circuit
Page 125 and 126: I n1 : i in I n2 -I n1 i scin ( sCi
Page 129 and 130: I nRf : 5.2 Developing an Analytic
Page 131 and 132: DC transimpedance gain: Pole locati
Page 133 and 134: Frequency (MHz) 500 450 400 350 300
Page 135 and 136: Pole frequencies(MHz) 500 450 400 3
Page 137 and 138: Optimizing Sensitivity 5.2 Developi
Page 141 and 142: Transimpedance Volts dB (lin) Gain
Page 143: CHAPTER 6 Implementation and Experi
Page 147 and 148: 6.1 A 1V Optical Receiver Front-End
Page 149 and 150: 6.1.2 Experimental Results 6.1 A 1V
Page 151 and 152: Gain(dB) 0 −1 −2 −3 −4 −5
Page 159 and 160: Clock signal of voltage doubler Eye
Page 161 and 162: 6.2 Variable-Gain Transimpedance Am
Page 163 and 164: 6.2.2 Experimental Results 6.2 Vari
Page 165 and 166: 6.3 Summary and State-of-the-Art Co
Page 167 and 168: Reference Outputs Technology Supply
Page 169 and 170: CHAPTER 7 Conclusions 7.1 SUMMARY A
Page 171 and 172: 7.2 Future Work 165 The significanc
Page 173 and 174: 7.2 Future Work 167 supply and subs
Page 175 and 176: v s i ti that part of the SFG for Q
Page 177 and 178: Thus, P1 ′ = b = 500Ω ∆1 ′
Page 179 and 180: itive representation of circuit dyn
Page 181 and 182: Bipolar Transistor i scb Z b v b b
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CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

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