CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

6.1.2 Experimental Results
6.1 A 1V Optical Receiver Front-End 143
A micrograph of the fabricated test chip is shown in Figure 6.8. The chip measures
1.0mm × 1.6mm and occupies an active area of 0.13mm . The main signal
2
path runs through the centre of the chip, from left to right. The bias voltage doubler
was placed in the far lower corner, away from the output buffer and output driver to
minimize noise coupled through parasitics.
The power consumption of the 1V front-end circuit is 1mW. The power con-
sumption of the 3V test circuitry is 45mW, and is essentially due to the output
buffer. An external 1pF capacitor was used to model the photodiode during electri-
cal testing, while a Mitel 1A354 PIN photodiode was used to construct the actual
optical link. The typical capacitance of the photodiode is 1pF for a bias voltage of
1V or more.
Frequency Response Measurements
In-
Vbias
M5
3 V
M1 M2
30 uA
M3 M4
In+
Iout
M1,2 = 5/0.8
M3,4 = 10/0.6
M5 = 20/0.8
Figure 6.7 Input test transconductor circuit.
The measured frequency response of the output buffer with source follower is
shown in Figure 6.9. The buffer has a loss of 4dB at the midband frequency of
20MHz, and its gain remains within +0.5dB and -3dB from 1MHz to 100MHz. The
remaining frequency responses presented for this chip take into account the