CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

3.1 A Differential Transimpedance Amplifier with Wide Dynamic Range 49
In order to keep the power dissipation below 10 mW, we limit the tail current of the
transimpedance amplifier’s input differential pair to 800 µA. This sets the maximum
input current to 400 µA. If we define the dynamic range of the amplifier as the ratio
of the 44nA noise floor obtained at its maximum sensitivity, to its maximum input
current of 400µA, this preamplifier has a dynamic range of 79.2 dB (electrical) or
39.6 dB (optical).
With a transimpedance gain of 500Ω, a 400 µA current produces a 200 mV out-
put voltage. Hence, the variable-transimpedance amplifier is designed to provide
gains from 20 kΩ (86 dBΩ) downto500Ω (54 dBΩ), representing a gain range of
32 dB. The simulation results shown in Figure 3.5 were obtained using the pass
transistor arrays described below. The results verify that the frequency response of
the amplifier is well behaved across the gain range. The simulated bandwidth is also
well regulated, varying only within a factor of two (i.e., from 68 MHz to 130MHz)
while the gain varies by a factor of 40 (32dB). The drop in bandwidth at the lowest
gain setting can be attributed to the increased significance of and on the
transimpedance gain of the internal second-stages. Strictly speaking, the transim-
pedance gain of these stages is proportional to ( 1 ⁄ gm56 , – R fa, b)
, and not simply
– R fa, b as assumed in the earlier discussion of the loop gain.
The four variable resistors of the transimpedance amplifier are identical. In
order to realize the desired gain range, each resistor is comprised of three pairs of
pass transistors as illustrated in Figure 3.6a. Each pass transistor can either be
turned off or set to one of two resistance values by controlling the gate bias voltages
as shown in the inset of Figure 3.6b. With three differently scaled pass transistors,
each having three settings, the digitally-controlled pass-transistor array has the abil-
ity to realize = 27 different resistance values. In order to maximize linearity,
3 3
complementary n- and p-channel MOSFETs are used, and the n-wells of the p-chan-
nel devices are tied to the output of the array to eliminate the body effect. A penalty
in speed of about 40% is incurred as a result of the added capacitance due to the n-
wells. Simulations show that the variable resistor remains within ± 10 % of its nom-
inal value for voltage drops within ±
0.3V .
g m5
g m6