CMOS Optical Preamplifier Design Using Graphical Circuit Analysis

3.3 A Low-Voltage Transimpedance Amplifier 62
of the amplifier. In practice, we need to derive a set of relations that embody the
essence of the circuit and characterize its design trade-offs. DPI/SFG analysis has
the potential to fulfill this requirement. The method is presented in Chapter 4, and
its application to the low-voltage transimpedance amplifier is presented in Chapter
5. Before proceeding, however, we need to conclude this section by discussing one
final design challenge for the low-voltage transimpedance amplifier: the implemen-
tation of the feedback resistor.
3.3.1 Dynamic Gate Biasing
Transimpedance (dB ohms)
80
70
60
50
40
30
20
10
10 0
0
10 1
Frequency (MHz)
Figure 3.17 Simulated frequency responses of four low-voltage transimpedance
designs with 3 dB bandwidths as indicated.
The variable feedback resistor of the transimpedance amplifier can be imple-
mented using either an NMOS or PMOS transistor operating in the linear region. An
NMOS device is preferred, however, because its decreased resistance under large
negative-going signals realizes soft limiting that further enhances the dynamic
range of the preamplifier. Biasing the gate of the NMOS device is a challenge. As
illustrated by the typical bias voltages in Figure 3.12, the source and drain of device
R f
60MHz
80MHz
70MHz
are already biased near the supply. For a 1V supply and without low-threshold
devices, a charge pump is required to bias the gate above the available supply. In
10 2
160MHz
10 3