3D Time-of-flight distance measurement with custom - Universität ...

DEMODULATION PIXELS IN CMOS/CCD 103
no parasitic charge will be integrated. This complete procedure can be repeated
until the amount of charge collected in the readout-CCD is large enough for a
sufficient SNR. Now the acquired sampling points can be transported to the
detection stage by clocking the readout-CCD. Each pixel has its own detection
stage (APS-concept, active pixel sensor) that can be selected for readout with an
address decoder.
A general problem in using CCD technology is the CCD’s speed performance. The
larger the length of a CCD gate, the longer the charge carriers need to travel from
this gate into the neighboring CCD gate. In Chapter 3 we have discussed that (1)
thermal diffusion, (2) self-induced drift (Coulomb forces) and (3) movement in an
electrical field (fringing field) are the only transport mechanisms for free charge
carriers in a semiconductor. Of these three the only directed and thus predictable
mechanism is the movement in a fringing field, the others being statistical
processes. Fringing fields, however, strongly depend on the semiconductor’s
impurity concentration, which is orders of magnitudes higher in the CMOS process
that we used than in a real CCD-process, used for commercial CCD sensors.
Therefore, in our CMOS-CCDs the fringing fields only extend to a very small region
between two adjacent gates. The transfer efficiency, only caused by thermal
diffusion, decreases with the square root of the gate length. This is why, for good
separation efficiency, the CCD gates have to be as short as possible, especially in
our CMOS/CCD process. For the same reason the size of the photogate may not
be chosen too large, otherwise the photoelectrons do not arrive in the pipeline-CCD
in time and the demodulation efficiency decreases. This limits the fill factor that can
be realized [CAR, SZ2].
In order to transfer charge-packets from the pipeline CCD into the readout CCD,
transfer gates had to be inserted between both CCD lines. Since only two polylayers
are available and we have to follow special design rules, the insertion of
transfer gates forces the layout of relatively long gates in the pipeline CCD. This
stands in contradiction to our requirement for a high transport speed and a high fill
factor. The advantage of this pixel compared to other implementations is the
possibility of realizing any number of storage sites. For this reason we call it the
“multitap-approach”. It has been introduced as an 8-tap pixel in [SP2] but has also
been realized with 16 taps for a special application. A larger number of storage
sites offers the possibility of operating a TOF-ranger with more complex modulation