3D Time-of-flight distance measurement with custom - Universität ...

IMAGING TOF RANGE CAMERAS 157
gate drivers (CCD load plus load capacitors) on the camera board. This rise/fall
time of the CCD gate signals influences the efficiency of the charge transfer (c.f.
[SP4]) and the effective ON/OFF shutter ratio of the demodulation pixels.
I
II
Coarse amplitude adjustment
Signal recovery
digital TTL
signal from
sequencer
I
5 V
0 V
5 V
0 V
74AC14
Pulse width adjustment
II
LM317
voltage
regulator
4.5 V - 15 V
driver supply
voltage
III
Gate
IV
15p
driver
22Ω
330Ω
200Ω
P1: 2kΩ
III
IV
trigger level of gate driver
0 V
Coarse amplitude
0 V
P2: 1kΩ
Amplitude fine tuning
and
Adjustment of rise/fall time
V
C 2
C 1
10Ω
V
to CCD gate
DC and AC fine tuned driving signal
P1
P2, C 1 /C 2 ,
coarse voltage slope:
C 1 + C 2
Figure 6.4 Driver circuitry including signal recovery (I, II), pulse width
adjustment (III, IV), coarse amplitude adjustment (IV) and fine
amplitude tuning (V). For the fine-tuning of the signal amplitude a
capacitive (AC) and ohmic (DC) voltage divider is used. The
dimensions of these capacitors and resistors determine the signal
slope. (RC low-pass).
The driver board illustrated in Figure 6.3 contains 24 separate CCD driver
channels. Eight of these channels offer the above described pulse width and signal
slope adjustment. The remaining 16 channels can be adjusted in amplitude by the
coarse amplitude setting of the gate drivers and in signal slope by an additional
capacitive load. For high flexibility, the discrete capacitors are plugged into sockets
rather than being soldered (c.f. Figure 6.3 left). In addition, nine different DC
signals can be provided to the PhotoASIC, four of which are targeted for use as