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3D Time-of-flight distance measurement with custom - Universität ...

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74 CHAPTER 3<br />

amount <strong>of</strong> the charge packet that remains after the transport losses δ resulting from<br />

the transport from one pixel to the next. One pixel mostly consists <strong>of</strong> three or four<br />

CCD gates (three- / four-phase CCDs), however, also two-phase or even onephase<br />

CCDs have been reported (TEU).<br />

( − δ)<br />

CTE = 1<br />

Equation 3.21<br />

After transportation <strong>of</strong> the charge packet by N pixel positions, the following share <strong>of</strong><br />

the original charge remains:<br />

( ) N<br />

1−<br />

N<br />

CTE = δ<br />

Equation 3.22<br />

Typical CCD processes <strong>of</strong>fer CTE values between 0.9999 and 0.99999. The<br />

following table shows the influence <strong>of</strong> both CTE and number <strong>of</strong> charge transfers<br />

(number <strong>of</strong> pixels) on the remaining charge packet.<br />

CTE=0.99 CTE=0.999 CTE=0.9999 CTE=0.99999<br />

N=10 90% 99% 99.9% 99.99%<br />

N=100 37% 90% 99% 99.9%<br />

N=1000 0% 37% 90% 99%<br />

Remaining charge after N transfers for different CTE values.<br />

The CCDs as we have described them so far are called surface channel CCDs<br />

(SCCD). As can be seen in Figure 3.7 (b) the potential minimum in the vertical<br />

direction for the classical MOS diode in deep depletion or strong inversion mode is<br />

located directly at the junction between semiconductor and gate oxide. Since the<br />

photoelectrons tend to stay at the potential minimum, the charge transport, which is<br />

due to a superimposed potential difference in the horizontal direction, takes place at<br />

the junction between semiconductor and oxide surfaces. Unfortunately, this junction<br />

region is characterized by charge traps (caused by lattice mismatch, surface states<br />

and impurities), which typically capture free electrons and randomly release them at<br />

later times. This is one main technical limitation for a good CTE in SCCDs.

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