3D Time-of-flight distance measurement with custom - Universität ...

SOLID-STATE IMAGE SENSING 61
Width of depletion layer (um)
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Number of integrated electrons
Figure 3.9 MOS photogate: Depletion width versus number of integrated free
electrons. (Effective gate voltage:10 V, substrate doping 4⋅10 14 cm -3 ,
gate size: 10 µm x 5 µm, oxide thickness: 40 nm).
Free charge carriers (electron hole pairs) are generally generated both optically and
thermally. It is, however, not possible to distinguish between optically generated
and thermally generated electrons. Both are integrated in the same potential
bucket. The thermal generation is therefore an unwanted effect (dark current) which
is sometimes reduced by cooling the CCD devices.
At this point we also understand the relatively large voltage requirements for CCDs.
The larger the voltages applied to the CCD gates, the higher the CCD’s charge
handling capability is. High voltages, on the other hand, increase the risk of oxide
break-through. This again is the reason why CCD processes use relatively thick
oxides, making them less suited for the realization of good MOS transistors.
Most CCDs have transparent photogates of polysilicon and are illuminated from the
front side (as the CCDs in this work). The polysilicon gates cause some additional
losses in quantum efficiency, especially in the blue (short wavelengths) and also
additional thin film interference peaks. Figure 3.10 shows the quantum efficiency
measurements of (CCD-) photogates (poly1 and poly2 photogates) realized in
2.0µm Orbit CMOS/CCD process, the process we used in the framework of this
dissertation for the realization of the demodulation pixels.