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3D Time-of-flight distance measurement with custom - Universität ...

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154 CHAPTER 6<br />

VCC<br />

GND<br />

VCC<br />

R 4.7k<br />

Connector<br />

to program<br />

PIC (F877)<br />

GND<br />

4<br />

PICreset<br />

clock_P 13(30)<br />

ITS<br />

FRAME 7<br />

PIX 6<br />

GND 3, 4<br />

PIC<br />

16F877/C74<br />

DIP or (TQFP)<br />

1(18)<br />

10(27) RE2<br />

GND 12,31(6,29)<br />

VCC 11,32(7,28)<br />

RC0 15(32)<br />

Connector<br />

to EPPI<br />

RA5 7(24)<br />

RA4 6(23) FRAME<br />

RA3 5(22)<br />

RA2 4(21) 3 status signals<br />

RA1 3(20)<br />

PIX<br />

VCC<br />

R 4.7k<br />

TAP0<br />

TAP1<br />

IE<br />

RE1 9(26) ST2 2 additional status signals<br />

RE0 8(25) ST1<br />

RA0 2(19) LED_P<br />

RB0 33(8) row0<br />

RB1 34(9) row1<br />

RB2 35(10) row2<br />

RB3 36(11) row3<br />

RB4 37(14) row4<br />

RB5 38(15) PGL<br />

RB6 39(16) PGR<br />

RB7 40(17) INTG<br />

col0<br />

RC1 16(35) col1<br />

RC2 17(36) col2<br />

RC3 18(37) col3<br />

RC4 23(42) col4<br />

RC5 24(43) col5<br />

RC6 25(44) free1<br />

RC7 26(1) free2<br />

RD0 19(38) res0<br />

RD1 20(39) res1<br />

RD2 21(40) res2<br />

RD3 22(41) res3<br />

RD4 27(2) res4<br />

RD5 28(3) free3<br />

RD6 29(4) free4<br />

RD7 30(5) free5<br />

16 (slow) outputs<br />

VCC 1<br />

SDO 2<br />

SDI 3<br />

ispEN 4<br />

5<br />

MODE<br />

GND<br />

SCLK<br />

Crystal<br />

80MHz<br />

GND 7<br />

8 MCLK<br />

VCC 14<br />

Connector<br />

to program<br />

LATTICE<br />

6<br />

7<br />

8<br />

FREE-<br />

I/O's<br />

ispEN<br />

SDI<br />

SDO<br />

SCLK<br />

MODE<br />

TAP0<br />

TAP1<br />

IE<br />

11<br />

65<br />

14<br />

16<br />

39<br />

60<br />

37<br />

67<br />

68<br />

69<br />

ST2 58<br />

ST1 57<br />

LED_P 59<br />

ROW0 81<br />

ROW1 80<br />

ROW2 79<br />

ROW3 78<br />

ROW4 85<br />

PGL_P 84<br />

PGR_P 83<br />

INTG 82<br />

GND 1, 22, 43, 64<br />

VCC 21, 65<br />

41<br />

42<br />

43<br />

44<br />

45<br />

46<br />

47<br />

48<br />

72 LED_L<br />

91 ROW0<br />

92 ROW1<br />

93 ROW2<br />

94 ROW3<br />

95 ROW4<br />

96 PGL_L<br />

97 PGR_L<br />

98 INTG<br />

17<br />

HEX-<br />

18<br />

19<br />

20<br />

35<br />

34<br />

73 PIC_CLK<br />

Connector<br />

to LEDs<br />

LED_L 3<br />

GND 2<br />

+19.5V 1<br />

+8V 4<br />

70 FUTURE_2<br />

71 FUTURE_1<br />

28<br />

29<br />

30<br />

31<br />

32<br />

33<br />

21<br />

22<br />

23<br />

40<br />

86<br />

90<br />

FREE-<br />

SWITCH<br />

FREQ-<br />

SWITCH<br />

SWITCH<br />

6 x Control LED<br />

red<br />

green<br />

red<br />

green<br />

red<br />

green<br />

Figure 6.2 Digital high-speed sequencer: Block diagram.<br />

20, 10,<br />

4, 2 MHz<br />

TP<br />

TP<br />

SMA<br />

BNC<br />

SMA<br />

BNC<br />

DC/DC<br />

+5V, +8V<br />

POWER<br />

VCC (+5V)<br />

Connector<br />

to camera<br />

1 ROW0<br />

2 ROW1<br />

3 ROW2<br />

4 ROW3<br />

5 ROW4<br />

6 PGL_L<br />

7 PGR_L<br />

8 INTG<br />

9<br />

COL0<br />

10<br />

COL1<br />

11<br />

COL2<br />

12<br />

COL3<br />

13<br />

COL4<br />

14<br />

COL5<br />

15<br />

(-)<br />

16<br />

(-)<br />

17<br />

RES0<br />

18<br />

RES1<br />

19<br />

RES2<br />

20<br />

RES3<br />

21<br />

RES4<br />

22<br />

(-)<br />

23<br />

(-)<br />

24<br />

(-)<br />

GND 25, 26, 31, 32<br />

+19.5V 37, 38<br />

VCC 39, 40<br />

33 (ana out) N.C.<br />

34 (AGND) N.C.<br />

In Figure 6.2 we show the block diagram <strong>of</strong> the sequencer board. With several<br />

freely programmable control switches for both the CPLD and the microcontroller,<br />

the board <strong>of</strong>fers flexible adaptation to different needs. For example, it can be<br />

programmed in such a way that the integration time or the readout speed for the<br />

single pixels can be changed during operation by different switches. Other<br />

variations are possible. A total number <strong>of</strong> eight (+1 for the LED control) fast control<br />

signals (80 MHz) can be generated by the CPLD (or simply fed through the CPLD if<br />

the microcontroller should take control). Additionally, the operation mode <strong>of</strong> the<br />

CPLD can be controlled by the microcontroller via five separate status lines.<br />

GND<br />

+8V<br />

+ 19.5V<br />

GND<br />

19.5V<br />

19.5V<br />

GND

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