3D Time-of-flight distance measurement with custom - Universität ...

DEMODULATION PIXELS IN CMOS/CCD 119
potential
OUTG
2 V
IG PGL PGM PGR
10.7 V 8.5 V 10 V 10 V
Figure 5.9 Connection between CCD-saturation (full well capacity) and
saturation of the output stage.
Linearity of the output stage
In Section 2.2.3 we already discussed the insensitivity of the 4-tap algorithm to
linear or quadratic distortions in the transfer characteristics. However, the algorithm
is sensitive to higher order non-linearities. For this purpose we measure the
linearity of the complete analog and digital conversion chain, containing the output
stage implemented on the demodulation pixel chip and the additional analog
electronics of the camera board and A/D conversion unit. This can be done by
illuminating the pixels with a highly accurate, constant light source and measuring
the output voltage swing versus the integration time. We choose a maximum
integration time of 50 ms and we measure 22 points with an increment of 2.3 ms in
integration time.