3D Time-of-flight distance measurement with custom - Universität ...

DEMODULATION PIXELS IN CMOS/CCD 117
quantities quantum efficiency, conversion capacitance and amplification can be
measured directly or independently from each other in the present implementation.
Since we never know the exact process parameters, we can only roughly estimate
amplification and conversion capacitance with an accuracy of about ± 10%:
Conversion capacitance: Cc = 40 fF
Amplification of SF stage: ASF = 0.9
Quantum efficiency at 630nm: 65%
� Sensitivity:
� Responsivity:
q
S = ASF
=3.6 µV/electron
Cc
q
R( λ ) = QE(
λ)
⋅ S = QE(
λ)
⋅ ASF
⋅ =2.35 µV/photon @ 630 nm
Cc
With the measurement conditions listed in MCD02 in the appendix we measure an
output voltage swing of 3.60 V. The theoretical calculations (all parameters in
MCD02) predict a swing of 3.25 V, which agrees very well with the measurement
(within the expected uncertainty range of ± 10%).
Saturation of output stage and CCD gates
The maximum signal (charge) that can be handled by a CCD structure is limited by
two independent (saturation) mechanisms. Firstly the charge must not exceed the
CCD gate’s charge handling capability and secondly the output voltage swing
caused by the signal charge must be within the operation range of the output
amplifier. The charge handling capability is essentially influenced by the voltage
difference between the single CCD gates (Qmax=Cgate⋅∆Vmax). A high voltage
difference allows more charge carriers to be integrated than a low voltage
difference.
It is the purpose of this section to investigate the voltage difference between the
integration gate and the modulated photogate that defines a charge handling
capability just leading to saturation of the output stage. In general, we expect the
demodulation contrast to increase with high voltage amplitudes on the modulated
photogates. It is obvious, however, that for a certain modulation amplitude,
depending on the actual voltage of the integration gate IG and the amount of