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3D Time-of-flight distance measurement with custom - Universität ...

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78 CHAPTER 3<br />

charge carriers the CTE decreases due to the missing or at least reduced<br />

contribution <strong>of</strong> self-induced drift on the charge transport; also trapping is a more<br />

serious problem for a small number <strong>of</strong> electrons to transport. [CAR] gives a very<br />

detailed description <strong>of</strong> how different parameters influence the CTE <strong>of</strong> a CCD.<br />

Today’s CCDs are realized <strong>with</strong> two or three different polysilicon layers. With these<br />

layers it is possible to overlap the single CCD gates in a small area. This leads to<br />

very thin gaps between the single gates, small enough that no potential barriers<br />

arise between the gates, which would possibly prohibit a complete charge transfer.<br />

(a)<br />

gate-poly<br />

metal<br />

diffusion<br />

substrate<br />

field oxide (thick)<br />

2nd-poly<br />

gate oxide (thin)<br />

poly-poly capacitor in CMOS<br />

potential<br />

5V<br />

(c)<br />

CCD in CMOS <strong>with</strong><br />

overlapping poly layers<br />

Figure 3.21 SCCD realization <strong>with</strong> a 2 poly MOS process: SCCD <strong>with</strong> overlapping<br />

poly layers (poly: polysilicon).<br />

Many available CMOS processes <strong>of</strong>fer two polysilicon layers. However the design<br />

rules prohibit the realization <strong>of</strong> transistor gates <strong>with</strong> the second poly layer. This<br />

10V<br />

(b)

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