3D Time-of-flight distance measurement with custom - Universität ...

IMAGING TOF RANGE CAMERAS 169
6.3 3D range camera
In addition to the 1-tap pixel realization in a 108-pixel line sensor, we also
implemented it in an array of 64 x 25 pixels. We describe the chip architecture, the
camera realization and some measured 3D images in this section.
6.3.1 64 x 25 pixel lock-in image sensor
The 64 x 25 pixel TOF-imager was fabricated in ORBIT 2.0 µm CMOS/CCD
technology using the American MOSIS prototyping service.
Chip layout and architecture
As for the realization of the line sensor, we used a TINY chip size (2 mm x 2 mm).
The 1600 pixels can be randomly accessed by an address decoder; the reset is
performed row-wise. The chip architecture and a micrograph of the chip are shown
in Figure 6.15.
Electrical low-pass characteristic of the modulated photogates (RC string)
We have shown in Section 6.2.1 that the serial connection of the CCD modulation
gates results in an RC string that limits the maximum demodulation frequency,
especially if the gates (i.e. the RC string) are connected only from one side. For the
line sensor we could increase the electrical cut-off frequency by a factor of 30 by
additionally connecting the CCD gates with metal wires at 3 points within the chain.
This is not possible for the image sensor, which is introduced here, since the
additional metal wires would drastically increase the pixel size and thus lower the
optical fill factor. For the smaller number of pixels per line (64 instead of 108) the
situation is, however, not as critical and the connection of the CCD gates from two
sides results in a sufficiently fast time response. The SPICE simulation results are
shown in Figure 6.16. The gate size of the modulation gates is 21 µm by 6 µm in
this imager realization. This leads to a typical ohmic resistance of 75 Ω and a
capacitance of 107 fF. The 3 dB cut-off frequency for the slowest gate is 55 MHz.