TMPM330 - Keil

Under development
The block diagram of this mode is shown below.
TB0IN0
φT1
φT4
φT16
TB0RG0-WR
Selector
Selector
TB0CR
16-bit comparator
TB0RG0
Register buffer 0
16-bit up-counter UC0
Clear
F/F
(TB0FF0)
Match
Internal data bus
TMPM330 (rev 0.4)8-28
TB0RUN
TB0OUT (PPG output)
16-bit comparator
TB0RG1
Register buffer 1
Fig. 8-4 Block Diagram of 16-bit PPG Mode
TMPM330
Each register in the 16-bit PPG output mode must be programmed as listed below.
7 6 5 4 3 2 1 0
TB0EN ← 1 X X X X X X X Starts the TMRB0 module.
TB0RUN ← X X X X X 0 X 0 Stops the TMRB0 module.
TB0RG0 ← * * * * * * * * Specifies a duty. (16 bits *32-bits for register)
← * * * * * * * *
TB0RG1 ← * * * * * * * * Specifies a cycle. (16 bits *32-bits for register)
← * * * * * * * *
TB0CR ← 1 0 X 0 0 0 0 0 Enables the TB0RG0 double buffering.
(Changes the duty/cycle when the INTTB0 interrupt is
generated)
TB0FFCR ← X X 0 0 1 1 1 0 Specifies to trigger TB0FF0 to reverse
when a match with TB0RG0 or TB0RG1 is detected,
and sets the initial value of TB0FF0 to "0."
TB0MOD ← 0 0 1 0 0 1 * * Designates the prescaler output clock as the input clock,
(** = 01, 10, 11) and disables the capture function.
PICR
PIFR1
←
←
−
−
−
-
−
−
−
−
−
−
−
−
−
−
1
1
Assigns PI0 to TB0OUT
TB0RUN ← * * * * * 1 X 1 Starts TMRB0
X; Don’t care −; no change
16-bit Timer/
Event Counters (TMRBs)