TMPM330 - Keil

(3) Receive Buffer Overrun
Under development
TMPM330 (rev0.4)11-27
TMPM330
A receive buffer overrun interrupt is generated when the next data reception is completed before
reading the data stored in the receive buffer.
The interrupt sets the CECRSTAT bit.
(4) Waveform Error
Beginning of ACK bit
A waveform error occurs when waveform error detection is enabled in CECRCR3. Detecting a
waveform, which does not identical to the defined, results in the waveform error. The interrupt is
generated.
The interrupt sets the CECRSTAT bit.
(5) Suspending Receive Error Interrupt
2.0ms
End of “0”
output
Detection period
You can specify if a maximum cycle error, a buffer overrun and a waveform error are suspended or
not without generating an interrupt at error detection. This can be set in the CECRCR1
bit. To enable the setting, a timeout setting with the CECRCR1 bit is
required.
Under suspend-enable condition, if CEC keeps receiving the next bit and the entire reception
including the ACK bit is completed, CEC generates an interrupt after a reversed ACK response is
executed. “1” is set to the bits of the CECRSTAT register: the bit that indicates the
reception completion, and the bits corresponding to the detected errors.
If the reception of the next bit is interrupted, CEC starts to measure the timeout period, and an
interrupt is generated after the timeout. “1” is set to the bits of the CECRSTAT register corresponding
to the detected error.
The timeout is measured from the end of the last bit received as is the case with wait time of a bus
to be free in transmission.
0.3ms
CEC