TMPM330 - Keil

Receiving data
SCLK output mode
Receive data
write timing
SCLK0 output
RXD0
(INTRX0 interrupt request)
Receive data
write timing
SCLK0 output
RXD0
(INTRX0 Interrupt request)
RBFULL
Receive data
write timing
SCLK0 output
RXD0
(INTRX0 Interrupt request)
RBFULL
Under development
TMPM330 (rev 0.4) 9-41
TMPM330
In the SCLK output mode, if SC0MOD2 = “0” and receive double buffering is
disabled, a synchronous clock pulse is output from the SCLK0 pin and the next data is
shifted into receive buffer 1 each time the CPU reads received data. When all the 8 bits
are received, the INTRX0 interrupt is generated.
The first SCLK output can be started by setting the receive enable bit SC0MOD0
to “1.” If the receive double buffering is enabled with SC0MOD2 set
to “1,” the first frame received is moved to receive buffer 2 and receive buffer 1 can
receive the next frame successively. As data is moved from receive buffer 1 to receive
buffer 2, the receive buffer full flag SC0MOD2 is set to “1” and the INTRX0
interrupt is generated.
While data is in receive buffer 2, if CPU/DMAC cannot read data from receive buffer 2
before completing reception of the next 8 bits, the INTRX0 interrupt is not generated
and the SCLK0 clock stops. In this state, reading data from receive buffer 2 allows data
in receive buffer 1 to move to receive buffer 2 and thus the INTRX0 interrupt is
generated and data reception resumes.
bit7
bit 0 bit 1
bit 6 bit 7
=“0” (if double buffering is disabled)
bit 0 bit 1
bit 6 bit 7
=“1” (if double buffering is enabled and data is read from buffer 2)
bit7
bit 0 bit 1
bit 6 bit 7
=“1” (if double buffering is enabled and data cannot be read from buffer 2)
Fig. 9-12 Receive Operation in the I/O Interface Mode (SCLK0 Output Mode)
bit 0
bit 0
Serial Channel (SIO)