TMPM330 - Keil

9.3.19 Signal Generation Timing
UART Mode:
Receive Side
Under development
TMPM330 (rev 0.4) 9-26
TMPM330
Mode 9-bit 8-bit with parity 8-bit, 7-bit, and 7-bit with parity
Interrupt generation Around the center of
timing
the 1st stop bit
Framing error Around the center of
generation timing the stop bit
Parity error generation
⎯
timing
Overrun error Around the center of
generation timing the stop bit
Around the center of the 1st
stop bit
Around the center of the stop
bit
Around the center of the last
(parity) bit
Around the center of the stop
bit
Around the center of the 1st stop bit
Around the center of the stop bit
Around the center of the last (parity) bit
Around the center of the stop bit
Transmit Side
Mode 9-bit 8-bit with parity 8-bit, 7-bit, and 7-bit with parity
Interrupt generation
timing
( = 0)
Interrupt generation
timing
( = 1)
② I/O interface mode:
Receive Side
Transmit Side
Just before the stop bit
is sent
Immediately after data
is moved to transmit
buffer 1 (just before
start bit transmission)
Just before the stop bit is sent Just before the stop bit is sent
Immediately after data is
moved to transmit buffer 1
(just before start bit
transmission).
Immediately after data is moved to transmit
buffer 1 (just before start bit transmission)
Interrupt generation timing SCLK output mode Immediately after the rising edge of the last SCLK
( = 0) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
falling edge mode, respectively).
Interrupt generation timing SCLK output mode Immediately after the rising edge of the last SCLK (just after data
( = 1)
transfer to receive buffer 2) or just after receive buffer 2 is read.
SCLK input mode Immediately after the rising edge or falling edge of the last SCLK (right
after data is moved to receive buffer 2).
Overrun error generation SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
timing
falling edge mode, respectively)
Interrupt generation timing SCLK output mode Immediately after the rising edge of the last SCLK
( = 0) SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
falling edge mode, respectively)
Interrupt generation timing SCLK output mode Immediately after the rising edge of the last SCLK or just after data is
( = 1)
moved to Transmit Buffer 1
SCLK input mode Immediately after the rising or falling edge of the last SCLK or just after
data is moved to Transmit Buffer 1
Under-run error generation
timing
SCLK input mode Immediately after the falling or rising edge of the next SCLK
(Note 1) Do not modify any control register when data is being sent or received (in a
state ready to transmit or receive).
(Note 2) Do not stop the receive operation (by setting SC0MOD0 = “0”) when
data is being received.
(Note 3) Do not stop the transmit operation (by setting SC0MOD1 = “0”)
when data is being transmitted.
Serial Channel (SIO)