TMPM330 - Keil

Command
sequence
(6) List of Command Sequences
First bus
cycle
Under development
Table 17-18 Flash Memory Access from the Internal CPU
Second bus
cycle
Third bus
cycle
Fourth bus
cycle
TMPM330 (rev 0.4)17-51
Fifth bus
cycle
Sixth bus
cycle
TMPM330
Seventh bus
cycle
Addr. Addr. Addr. Addr. Addr. Addr. Addr.
Data Data Data Data Data Data Data
Read
0xXX - - - - - -
0xF0 - - - - - -
Read/Reset
0x54XX 0xAAXX 0x54XX RA - - -
0xAA 0x55 0xF0 RD - - -
ID-Read
0x54XX 0xAAXX 0x54XX IA 0xXX - -
0xAA 0x55 0x90 0x00 ID - -
Automatic page 0x54XX 0xAAXX 0x54XX PA PA PA PA
programming
(note)
0xAA 0x55 0xA0
PD0 PD1
PD2 PD3
Automatic chip 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX -
erase 0xAA 0x55 0x80 0xAA 0x55 0x10 -
Auto
0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX BA -
Block erase (note) 0xAA 0x55 0x80 0xAA 0x55 0x30 -
Protection bit 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA
programming 0xAA 0x55 0x9A 0xAA 0x55 0x9A 0x9A
Protection bit 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA
erase 0xAA 0x55 0x6A 0xAA 0x55 0x6A 0x6A
Supplementary explanation
• RA: Read address
• RD: Read data
• IA: ID address
• ID: ID data
• PA: Program page address
PD: Program data (32 bit data)
After the fourth bus cycle, enter data in the order of the address for a page.
• BA: Block address
• PBA: Protection bit address
• 0x54xx: Substitutable by 0x55xx
(Note 1) Always set "0" to the address bits [1:0] in the entire bus cycle. (Recommendable setting
values to bits [7:2] are ”0”.)
(Note 2) Bus cycles are "bus write cycles" except for the second bus cycle of the Read command,
the fourth bus cycle of the Read/reset command, and the fifth bus cycle of the ID-Read
command. Bus write cycles are executed by 32-bit data transfer commands. The address
[31:16] in each bus write cycle should be the target flash memory address [31:16] of the
command sequence. Use "Addr." in the table for the address [15:0].
Flash Memory Operation