TMPM330 - Keil

(3) Cycle Error
Under development
Configure the CECRCR1 bits to detect a cycle error.
TMPM330 (rev0.4)11-20
TMPM330
You can specify the time to detect a cycle error for each sampling clock cycle between the ranges
of -4 to +3 cycles from the maximum or minimum time set in the CEC standard.
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start
bit. The received data is discarded.
(4) Point of Determining Data
Configure the CECRCR1 bit for the point of determining the data as “0” or “1”.
You can specify it per two sampling clock cycles between the ranges of + or - 6 cycles with approx.
1.05 ms from the bit start point.
(5) ACK Response
Configuring the CECRCR1 bit enables you to specify if logical “0” is sent or not as
an ACK response to the data block when destination address corresponds with the address set in
the logical address register.
The header block sends logical “0” as an ACK response regardless of the bit setting when
detecting the addresses corresponding.
(6) Receive Error Interrupt Suspend
Configure the CECRCR1 bit to specify if a receive error interrupt (maximum cycle
error, buffer overrun and waveform error) is suspended or not.
Setting “1” generates no interrupt at the error detection. If data continues to the ACK bit, an ACK
response is executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a
timeout, based on the setting in of the CECRCR1 register. After the ACK response or
the timeout determination, an interrupt is generated.
(7) Cycles to Identify Timeout
Configure the CECRCR1 bit to specify the time to determine a timeout.
This is used when the setting of a receive error interrupt suspension, which is specified in
CECRCR1 , is valid.
CEC