TMPM330 - Keil

9.4.11 RX FIFO status register
SC0RST
Under development
TMPM330 (rev 0.4) 9-36
TMPM330
7 6 5 4 3 2 1 0
bit Symbol ROR RLVL2 RLVL1 RLVL0
Read/Write R R R
After reset 0 0 0 0 0
Function
RX FIFO
Overrun
1:
Generate
d
“0” is read. Status of RX FIFO fill level
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
: Flags for RX FIFO overrun. When the overrun occurs, these bits are set to “1” (see note).
: Shows the fill level of RX FIFO.
(Note) The bit is cleared to “0” when receive data is read from the SC0BUF
register.
9.4.12 TX FIFO status register
SC0TST
7 6 5 4 3 2 1 0
bit Symbol TUR TLVL2 TLVL1 TLVL0
Read/Write R R R
After reset 1 0 0 0 0
Function
TX FIFO
Under run
1:Generat
ed
Cleared
by writing
FIFO
“0” is read. Status of TX FIFO fill level
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
: Flags for TX FIFO underrun. When the underrun occurs, these bits are set to “1” (see
note).
: Shows the fill level of TX FIFO.
(Note) The bit is cleared to “0” when transmit data is written to the SC0BUF
register.
Serial Channel (SIO)