TMPM330 - Keil

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Clear peripheral clock 0 (fgear) 1 (fc) Under development Table 9-2 Clock Resolution to the Baud Rate Generator @ = 40MHz Clock gear value 000 (fc) 100(fc/2) 101(fc/4) 110(fc/8) 000 (fc) 100(fc/2) 101(fc/4) 110(fc/8) Prescaler clock selection TMPM330 (rev 0.4) 9-6 Prescaler output clock resolution TMPM330 φT1 φT4 φT16 φT64 000(fperiph/1) fc/2 1 (0.05μs) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) 001(fperiph/2) fc/2 2 (0.1μs) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 010(fperiph/4) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 011(fperiph/8) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 100(fperiph/16) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 101(fperiph/32) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 000(fperiph/1) fc/2 2 (0.1μs) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 001(fperiph/2) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 010(fperiph/4) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 011(fperiph/8) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 100(fperiph/16) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 101(fperiph/32) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) fc/2 13 (204.8μs) 000(fperiph/1) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 001(fperiph/2) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 010(fperiph/4) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 011(fperiph/8) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 100(fperiph/16) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) fc/2 13 (204.8μs) 101(fperiph/32) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) fc/2 14 (409.6μs) 000(fperiph/1) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 001(fperiph/2) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 010(fperiph/4) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 011(fperiph/8) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) fc/2 13 (204.8μs) 100(fperiph/16) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) fc/2 14 (409.6μs) 101(fperiph/32) fc/2 9 (12.8μs) fc/2 11 (51.2μs) fc/2 13 (204.8μs) fc/2 15 (819.2μs) 000(fperiph/1) fc/2 1 (0.05μs) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) 001(fperiph/2) fc/2 2 (0.1μs) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 010(fperiph/4) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 011(fperiph/8) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 100(fperiph/16) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 101(fperiph/32) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 000(fperiph/1) - fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) 001(fperiph/2) fc/2 2 (0.1μs) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 010(fperiph/4) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 011(fperiph/8) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 100(fperiph/16) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 101(fperiph/32) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 000(fperiph/1) - fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) 001(fperiph/2) - fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 010(fperiph/4) fc/2 3 (0.2μs) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 011(fperiph/8) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 100(fperiph/16) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 101(fperiph/32) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) 000(fperiph/1) - - fc/2 5 (0.8μs) fc/2 7 (3.2μs) 001(fperiph/2) - fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) 010(fperiph/4) - fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) 011(fperiph/8) fc/2 4 (0.4μs) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) 100(fperiph/16) fc/2 5 (0.8μs) fc/2 7 (3.2μs) fc/2 9 (12.8μs) fc/2 11 (51.2μs) 101(fperiph/32) fc/2 6 (1.6μs) fc/2 8 (6.4μs) fc/2 10 (25.6μs) fc/2 12 (102.4μs) Serial Channel (SIO)
Under development (Note 1) The prescaler output clock φTn must be selected so that the relationship “φTn < fsys” is satisfied (so that φTn is slower than fsys). (Note 2) Do not change the clock gear while SIO is operating. (Note 3) The horizontal lines in the above table indicate that the setting is prohibited. TMPM330 (rev 0.4) 9-7 TMPM330 The serial interface baud rate generator uses four different clocks, i.e., φT1, φT4, φT16 and φT64, supplied from the prescaler output clock. Serial Channel (SIO)
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1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
Page 61 and 62: 7.1.3 Port C (PC0~PC3) Under develo
Page 63 and 64: 7.1.5 Port E (PE0~PE6) Under develo
Page 65 and 66: 7.1.6 Port F (PF0~PF7) Under develo
Page 67 and 68: 7.1.7 Port G (PG0~PG7) Under develo
Page 69 and 70: 7.1.8 Port H (PH0~PH7) Under develo
Page 71 and 72: 7.1.10 Port J (PJ0~PJ7) Under devel
Page 73 and 74: Under development Port K input enab
Page 75 and 76: 8.2 Differences in the Specificatio
Page 77 and 78: Configuration Under development TMP
Page 79 and 80: Registers 8.2.1 TMRB registers Spec
Page 81 and 82: Under development 8.2.1.1 TMRBn ena
Page 83 and 84: Under development 8.2.1.3 TMRB cont
Page 85 and 86: Under development 8.2.1.5 TMRB flip
Page 87 and 88: TBnIM (0x4001_0xx8) Under developme
Page 89 and 90: Under development 8.2.1.9 TMRB time
Page 91 and 92: Under development 8.3 Description o
Page 93 and 94: Under development TMPM330 (rev 0.4)
Page 97 and 98: • Register setting Under developm
Page 99 and 100: Under development 8.4 Description o
Page 101 and 102: Under development The block diagram
Page 103 and 104: Under development 8.6 Applications
Page 105 and 106: Prescaler output clock TB5IN0 pin i
Page 107 and 108: 9 Serial Channel (SIO) 9.1 Features
Page 109 and 110: • Mode 0 (I/O Interface mode) /LS
Page 111: Under development 9.3 Operation of
Page 115 and 116: Under development (Note 1) The pres
Page 117 and 118: • Example baud rate setting: Unde
Page 119 and 120: fc [MHz] Under development Table 9-
Page 123 and 124: Under development I/O interface mo
Page 125 and 126: • Handshake function Data write t
Page 127 and 128: 9.3.10 Transmit FIFO Buffer Under d
Page 129 and 130: 9.3.12 Parity Control Circuit 9.3.1
Page 131 and 132: Under development 9.3.17 Configurat
Page 133 and 134: Under development 9.4 Register Desc
Page 135 and 136: 9.4.4 Mode control register 0 SC0MO
Page 137 and 138: Under development : This is a statu
Page 141 and 142: 9.4.10 TX FIFO configuration regist
Page 143 and 144: 9.5 Operation in Each Mode 9.5.1 Mo
Page 145 and 146: SCLK input mode Under development T
Page 147 and 148: Receiving data SCLK output mode Rec
Page 149 and 150: Transmit and receive (full-duplex)
Page 151 and 152: SCLK input mode Under development T
Page 153 and 154: 9.5.2 Mode 1 (7-bit UART Mode) Unde
Page 155 and 156: 9.5.4 Mode 3 (9-bit UART) Under dev
Page 157 and 158: 10. Serial Bus Interface (SBI) Chan
Page 159 and 160: 10.2 Control Under development TMPM
Page 161 and 162: SBIxCR0 10.4 Control Registers in t
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Under development TMPM330 (rev 0.4)
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Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
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Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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