TMPM330 - Keil

5.4 System Clock Control
5.4.1 Initial Values after Reset
Under development
Reset initializes the system clock controller as follows.
High-speed oscillator : ON (oscillating)
Low-speed oscillator : ON (oscillating)
PLL (phase locked loop circuit) : OFF (stop)
High-speed clock gear : fc (no frequency dividing)
TMPM330 (rev0.4) 5-9
TMPM330
For example, when a 10-MHz oscillator is connected to the X1 or X2 pin, fsys becomes 10MHz after
reset.
Reset
Reset has been
performed.
NORMAL mode
PLL OFF
fosc = fc = fsys = fperiph
Fig. 5-4 Default State of System Clock
Fosc : Clock frequency to be input via the X1 and X2 pins
Fc : High clock frequency
Fsys : System clock frequency
Fperiph : Clock frequency selected by SYSCR1 (Clock to be input to the peripheral I/O
prescaler)
Clock/ Mode Control