TMPM330 - Keil

11.3.1.8 Detecting Error Interrupt
Under development
TMPM330 (rev0.4)11-26
TMPM330
Detecting an error during data reception causes an error interrupt, and CEC waits for the next start
bit. The received data is discarded.
It is possible to suspend a receive error interrupt (maximum cycle error, receive buffer overrun and
waveform error), continue reception and send the reversed ACK response.
You can check the interrupt factor by monitoring the bit of the CECRSTAT register corresponding
to the interrupt.
11.3.1.9 Details of Receive Error
(1) Cycle Error
Period between the falling edges of the two sequential bits is measured during reception. If the
period does not comply with the specified minimum or maximum value, a cycle error interrupt is
generated.
The maximum and minimum cycles are specified in the CECRCR1
bits. A cycle error can be detected for each sampling clock cycle between the ranges of -4 to +3
cycles from the minimum value (approx. 2.05 ms) or the maximum value (approx. 2.75 ms) defined
by the CEC standard.
The CECRSTAT bit or the bit is set if a cycle error interrupt is
generated.
The minimum cycle error causes CEC to output “0” for approx. 3.6 ms.
(2) ACK Collision
At an ACK response, detecting “0” after the specified period to output generates an ACK collision
interrupt or a minimum cycle error interrupt.
The ACK collision interrupt sets the CECRSTAT bit. The minimum cycle error
interrupt sets the CECRSTAT bit.
The following describes the period and method of detection.
Detection starts approx. 0.3 ms after the end of the period of outputting “0” and ends approx 2.0
ms from the starting point (the falling edge) of the ACK bit.
At 0.3 ms from the end of the period of outputting “0”, CEC checks if the CEC line is “0” or not. If it
is “0”, an ACK collision interrupt is generated. If it is “1”, and “0” is detected during the detection
period, the minimum cycle error interrupt is generated. The minimum cycle error causes CEC to
output “0” for approx. 3.6 ms.
CEC