TMPM330 - Keil

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Under development Table 10-2 Processing in Slave Mode State Processing 1 0 TMPM330 (rev 0.4) 10-24 TMPM330 1 1 0 Arbitration Lost is detected while the Set the number of bits in a data word to slave address was being transmitted and write the transmit data and the SBI received a slave address with the direction bit “1” transmitted by another master. into SBIxDBR. 0 1 0 In the slave receiver mode, the SBI received a slave address with the direction bit “1” transmitted by the master. 0 0 In the slave transmitter mode, the SBI Test LRB. If it has been set to “1,” that has completed a transmission of one means the receiver does not require data word. further data. Set to 1 and reset to 0 to release the bus. If has been reset to “0,” that means the receiver requires further data. Set the number of bits in the data word to and write the transmit data to the SBIxDBR. 1 1 1/0 Arbitration Lost is detected while a Read the SBIxDBR (a dummy read) to slave address is being transmitted, and the SBI receives either a slave address with the direction bit “0” or a general-call address transmitted by another master. set to 1, or write “1” to . 0 0 Arbitration Lost is detected while a slave address or a data word is being transmitted, and the transfer is terminated. 0 1 1/0 In the slave receiver mode, the SBI received either a slave address with the direction bit “0” or a general-call address transmitted by the master. 0 1/0 In the slave receiver mode, the SBI Set the number of bits in the data word has completed a reception of a data to and read the received data word. from SBIxDBR. Serial Bus Interface (SBI)
10.6.4 Generating the Stop Condition Under development TMPM330 (rev 0.4) 10-25 TMPM330 When SBIxSR is “1,” writing “1” to SBIxCR2 and “0” to causes the SBI to start a sequence for generating the stop condition on the bus. Do not alter the contents of until the stop condition appears on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released. After that, the SDA pin goes high, causing the stop condition to be generated. 7 6 5 4 3 2 1 0 SBIxCR2 ← 1 1 0 1 1 0 0 0 Generates the stop condition. “1” → “1” → “0” → “1” → SCL pin SDA pin (read) Fig. 10-18 Generating the Stop Condition Stop condition Serial Bus Interface (SBI)
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1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
Page 129 and 130: 9.3.12 Parity Control Circuit 9.3.1
Page 131 and 132: Under development 9.3.17 Configurat
Page 133 and 134: Under development 9.4 Register Desc
Page 135 and 136: 9.4.4 Mode control register 0 SC0MO
Page 137 and 138: Under development : This is a statu
Page 139 and 140: Under development TMPM330 (rev 0.4)
Page 141 and 142: 9.4.10 TX FIFO configuration regist
Page 143 and 144: 9.5 Operation in Each Mode 9.5.1 Mo
Page 145 and 146: SCLK input mode Under development T
Page 147 and 148: Receiving data SCLK output mode Rec
Page 149 and 150: Transmit and receive (full-duplex)
Page 151 and 152: SCLK input mode Under development T
Page 153 and 154: 9.5.2 Mode 1 (7-bit UART Mode) Unde
Page 155 and 156: 9.5.4 Mode 3 (9-bit UART) Under dev
Page 157 and 158: 10. Serial Bus Interface (SBI) Chan
Page 159 and 160: 10.2 Control Under development TMPM
Page 161 and 162: SBIxCR0 10.4 Control Registers in t
Page 163 and 164: Under development TMPM330 (rev 0.4)
Page 165 and 166: Under development Table 10-1 Base C
Page 167 and 168: SBIxBR0 bit Symbol I2SBI0 Under dev
Page 169 and 170: 10.5 Control in the I 2 C Bus Mode
Page 171 and 172: Under development 10.5.6 Configurin
Page 173 and 174: Master A Master B Under development
Page 175 and 176: Under development 10.6 Data Transfe
Page 177 and 178: SCL pin Write to SBIxDBR SDA pin I
Page 179: Slave mode ( = “0”) Under devel
Page 183 and 184: Under development 10.7 Control in t
Page 185 and 186: SBIxDBR SBIxCR2 Under development S
Page 187 and 188: 10.7.1 Serial Clock SCK pin output
Page 189 and 190: 10.7.2 Transfer Modes Under develop
Page 191 and 192: SCK pin SIOF SO pin bit 6 Under dev
Page 193 and 194: SCK pin (output) SO pin SI pin IN
Page 195 and 196: 11.2 Registers 11.2.1 Control Regis
Page 197 and 198: Under development 11.2.5 Software R
Page 199 and 200: Under development 11.2.7 Receive Bu
Page 201 and 202: Under development TMPM330 (rev0.4)1
Page 203 and 204: Under development 11.2.10 Receive C
Page 205 and 206: Under development 11.2.11 Transmit
Page 207 and 208: Under development 11.2.13 Transmit
Page 209 and 210: Under development 11.2.14 Receive I
Page 211 and 212: 11.3 Operations 11.3.1 Reception 11
Page 213 and 214: (3) Cycle Error Under development C
Page 215 and 216: (10) Waveform Error Detection Under
Page 217 and 218: 11.3.1.6 Data Sampling Point Under
Page 219 and 220: 11.3.1.8 Detecting Error Interrupt
Page 221 and 222: Under development TMPM330 (rev0.4)1
Page 223 and 224: 11.3.2.2 Preconfiguration Under dev
Page 225 and 226: 11.3.2.3 Starting Transmission Unde
Page 227 and 228: (2) ACK error Under development TMP
Page 229 and 230: Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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