TMPM330 - Keil

11.3.1.6 Data Sampling Point
Under development
The figure shown below illustrates a data sampling timing.
TMPM330 (rev0.4)11-24
TMPM330
With the CECRCR1 bit, you can specify a data sampling point per two sampling clock
cycles between the ranges of + or - 6 cycles from a reference point (approx. 1.05 ms).
0ms
11.3.1.7 ACK Response
Setting the CECRCR1 bit enables to specify if logical “0” is sent or not as an ACK
response to the data block when destination address corresponds with the address set in the logical
address register. The header block sends logical “0” as an ACK response regardless of the bit
setting when detecting the addresses corresponding.
The following lists the ACK responses.
“Yes” indicates that CEC outputs “0” as a response to the ACK signal from a transmission device
(ACK bit: logical “0”). “No” indicates that CEC does not output “0” as a response to the ACK signal
from a transmission device (ACK bit: logical “1”).
Register setting
“0”
(responding logical
CECRCR1
“0”)
“1”
(not responding
logical “0”)
0.6ms 1.5ms
0.85ms 1.05ms 1.25ms
Reference point for
data sampling
0.25ms
Recommended
period for data
sampling
0.25ms
Header block address Data block address
Conformity Discrepancy Conformity Discrepancy
Yes No
Yes No
No No
CEC