TMPM330 - Keil

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[1] Port [4/4] ADR Register name ADR Register name Under development ADR TMPM330 (rev.0.4) 16-5 Register name ADR 0x4000_0240 PJ 0x4000_0250 Reserved 0x4000_0260 0x4000_0270 0x4000_0241 0x4000_0251 “ 0x4000_0261 0x4000_0271 0x4000_0242 0x4000_0252 “ 0x4000_0262 0x4000_0272 0x4000_0243 0x4000_0253 “ 0x4000_0263 0x4000_0273 0x4000_0244 PJCR 0x4000_0254 0x4000_0264 0x4000_0274 0x4000_0245 0x4000_0255 0x4000_0265 0x4000_0275 0x4000_0246 0x4000_0256 0x4000_0266 0x4000_0276 0x4000_0247 0x4000_0257 0x4000_0267 0x4000_0277 TMPM330 Register name 0x4000_0248 PJFR1 0x4000_0258 0x4000_0268 0x4000_0278 PJIE 0x4000_0249 0x4000_0259 0x4000_0269 0x4000_0279 0x4000_024A 0x4000_025A 0x4000_026A 0x4000_027A 0x4000_024B 0x4000_025B 0x4000_026B 0x4000_027B 0x4000_024C 0x4000_025C 0x4000_026C PJPUP 0x4000_027C 0x4000_024D 0x4000_025D 0x4000_026D 0x4000_027D 0x4000_024E 0x4000_025E 0x4000_026E 0x4000_027E 0x4000_024F 0x4000_025F 0x4000_026F 0x4000_027F ADR Register name ADR Register name ADR Register name ADR 0x4000_0280 PK 0x4000_0290 0x4000_02A0 0x4000_02B0 0x4000_0281 0x4000_0291 0x4000_02A1 0x4000_02B1 0x4000_0282 0x4000_0292 0x4000_02A2 0x4000_02B2 0x4000_0283 0x4000_0293 0x4000_02A3 0x4000_02B3 0x4000_0284 PKCR 0x4000_0294 0x4000_02A4 0x4000_02B4 0x4000_0285 0x4000_0295 0x4000_02A5 0x4000_02B5 0x4000_0286 0x4000_0296 0x4000_02A6 0x4000_02B6 0x4000_0287 0x4000_0297 0x4000_02A7 0x4000_02B7 Register name 0x4000_0288 PKFR1 0x4000_0298 0x4000_02A8 0x4000_02B8 PKIE 0x4000_0289 0x4000_0299 0x4000_02A9 0x4000_02B9 0x4000_028A 0x4000_029A 0x4000_02AA 0x4000_02BA 0x4000_028B 0x4000_029B 0x4000_02AB 0x4000_02BB 0x4000_028C PKFR2 0x4000_029C 0x4000_02AC PKPUP 0x4000_02BC 0x4000_028D 0x4000_029D 0x4000_02AD 0x4000_02BD 0x4000_028E 0x4000_029E 0x4000_02AE 0x4000_02BE 0x4000_028F 0x4000_029F 0x4000_02AF 0x4000_02BF Table of Special Function Registers
[2] 16-bit timer [1/4] ADR Register name ADR Register name Under development ADR TMPM330 (rev.0.4) 16-6 Register name ADR 0x4001_0000 TB0EN 0x4001_0010 TB0FFCR 0x4001_0020 TB0RG0L 0x4001_0030 0x4001_0001 0x4001_0011 0x4001_0021 TB0RG0H 0x4001_0031 0x4001_0002 0x4001_0012 0x4001_0022 0x4001_0032 0x4001_0003 0x4001_0013 0x4001_0023 0x4001_0033 0x4001_0004 TB0RUN 0x4001_0014 TB0ST 0x4001_0024 TB0RG1L 0x4001_0034 0x4001_0005 0x4001_0015 0x4001_0025 TB0RG1H 0x4001_0035 0x4001_0006 0x4001_0016 0x4001_0026 0x4001_0036 0x4001_0007 0x4001_0017 0x4001_0027 0x4001_0037 0x4001_0008 TB0CR 0x4001_0018 TB0IM 0x4001_0028 TB0CP0L 0x4001_0038 0x4001_0009 0x4001_0019 0x4001_0029 TB0CP0H 0x4001_0039 0x4001_000A 0x4001_001A 0x4001_002A 0x4001_003A 0x4001_000B 0x4001_001B 0x4001_002B 0x4001_003B 0x4001_000C TB0MOD 0x4001_001C TB0UCL 0x4001_002C TB0CP1L 0x4001_003C 0x4001_000D 0x4001_001D TB0UCH 0x4001_002D TB0CP1H 0x4001_003D 0x4001_000E 0x4001_001E 0x4001_002E 0x4001_003E 0x4001_000F 0x4001_001F 0x4001_002F 0x4001_003F ADR Register name ADR Register name ADR Register name ADR 0x4001_0040 TB1EN 0x4001_0050 TB1FFCR 0x4001_0060 TB1RG0L 0x4001_0070 0x4001_0041 0x4001_0051 0x4001_0061 TB1RG0H 0x4001_0071 0x4001_0042 0x4001_0052 0x4001_0062 0x4001_0072 0x4001_0043 0x4001_0053 0x4001_0063 0x4001_0073 0x4001_0044 TB1RUN 0x4001_0054 TB1ST 0x4001_0064 TB1RG1L 0x4001_0074 0x4001_0045 0x4001_0055 0x4001_0065 TB1RG1H 0x4001_0075 0x4001_0046 0x4001_0056 0x4001_0066 0x4001_0076 0x4001_0047 0x4001_0057 0x4001_0067 0x4001_0077 0x4001_0048 TB1CR 0x4001_0058 TB1IM 0x4001_0068 TB1CP0L 0x4001_0078 0x4001_0049 0x4001_0059 0x4001_0069 TB1CP0H 0x4001_0079 0x4001_004A 0x4001_005A 0x4001_006A 0x4001_007A 0x4001_004B 0x4001_005B 0x4001_006B 0x4001_007B 0x4001_004C TB1MOD 0x4001_005C TB1UCL 0x4001_006C TB1CP1L 0x4001_007C 0x4001_004D 0x4001_005D TB1UCH 0x4001_006D TB1CP1H 0x4001_007D 0x4001_004E 0x4001_005E 0x4001_006E 0x4001_007E 0x4001_004F 0x4001_005F 0x4001_006F 0x4001_007F ADR Register name ADR Register name ADR Register name ADR 0x4001_0080 TB2EN 0x4001_0090 TB2FFCR 0x4001_00A0 TB2RG0L 0x4001_00B0 0x4001_0081 0x4001_0091 0x4001_00A1 TB2RG0H 0x4001_00B1 0x4001_0082 0x4001_0092 0x4001_00A2 0x4001_00B2 0x4001_0083 0x4001_0093 0x4001_00A3 0x4001_00B3 0x4001_0084 TB2RUN 0x4001_0094 TB2ST 0x4001_00A4 TB2RG1L 0x4001_00B4 0x4001_0085 0x4001_0095 0x4001_00A5 TB2RG1H 0x4001_00B5 0x4001_0086 0x4001_0096 0x4001_00A6 0x4001_00B6 0x4001_0087 0x4001_0097 0x4001_00A7 0x4001_00B7 0x4001_0088 TB2CR 0x4001_0098 TB2IM 0x4001_00A8 TB2CP0L 0x4001_00B8 0x4001_0089 0x4001_0099 0x4001_00A9 TB2CP0H 0x4001_00B9 0x4001_008A 0x4001_009A 0x4001_00AA 0x4001_00BA 0x4001_008B 0x4001_009B 0x4001_00AB 0x4001_00BB 0x4001_008C TB2MOD 0x4001_009C TB2UCL 0x4001_00AC TB2CP1L 0x4001_00BC 0x4001_008D 0x4001_009D TB2UCH 0x4001_00AD TB2CP1H 0x4001_00BD 0x4001_008E 0x4001_009E 0x4001_00AE 0x4001_00BE 0x4001_008F 0x4001_009F 0x4001_00AF 0x4001_00BF TMPM330 Register name Register name Register name Table of Special Function Registers
Page 1 and 2:
1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Page 123 and 124:
Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
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Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
Page 247 and 248: Under development 12.3.1.8 Receivin
Page 249 and 250: Remote control signal waveform (inp
Page 251 and 252: Remote control signal in phase meth
Page 253 and 254: 13.1 Registers Under development Th
Page 255 and 256: ADMOD1 Under development A/D Mode C
Page 261 and 262: ADREG2AL ADREG2AH ADREG3BL ADREG3BH
Page 263 and 264: ADREG6EL ADREG6EL ADREG6EL ADREG6EL
Page 265 and 266: ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
Page 267 and 268: 13.4 Description of Operations 13.4
Page 269 and 270: Under development TMPM330 (rev 0.4)
Page 271 and 272: Under development 3. Fixed channel
Page 273 and 274: 13.4.5 High-priority Conversion Mod
Page 275 and 276: Under development 14. Watchdog Time
Page 277 and 278: 14.3 Control Registers Under develo
Page 279 and 280: 14.4 Control Register Under develop
Page 281 and 282: 15.3 Control Register Under develop
Page 283 and 284: MINR Under development (2) Minute c
Page 285 and 286: DAYR DATER Under development (4) Da
Page 287 and 288: YEARR YEARR Under development (8) Y
Page 289 and 290: 15.5 Operational description (1) Re
Page 291 and 292: 3. Disabling the clock Under develo
Page 293 and 294: (2) 1Hz clock Under development TMP
Page 295 and 296: 16.1 Addresses [1] Port [1/4] ADR
Page 297: [1] Port 3/4] ADR Register name AD
Page 301 and 302: [2] 16-bit timer [3/4] ADR Registe
Page 303 and 304: Under development [3] Serial bus in
Page 305 and 306: [5] 10-bit A/D converter (A/DC) ADR
Page 307 and 308: [10] Remote control signal preproce
Page 309 and 310: Under development JEDEC compliant f
Page 313 and 314: User Boot Mode Under development (1
Page 315 and 316: (Step-5) Under development TMPM330
Page 319 and 320: 17.2.3 Single Boot Mode Under devel
Page 323 and 324: (1) Configuration for Single Boot M
Page 325 and 326: (5) Restrictions on internal memori
Page 327 and 328: Under development Table 17-7 Transf
Page 329 and 330: Under development Table 17-9 Transf
Page 331 and 332: (6) Operation of Boot Program Under
Page 335 and 336: Under development returns to the st
Page 337 and 338: Under development 3) Show Product I
Page 339 and 340: Under development 4) Chip Erase com
Page 341 and 342: 5) Acknowledge Responses Under deve
Page 343 and 344: Point A Point B Point C Point D Und
Page 345 and 346: Start Are all bytes the same? YES A
Page 347 and 348: (7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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