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TMPM330 - Keil

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(4) Settings of Reception Completion<br />

Under development<br />

<strong>TMPM330</strong> (rev0.4)12-16<br />

<strong>TMPM330</strong><br />

To complete data reception, settings of detecting the maximum data bit cycle and excess low width<br />

are required. If multiple factors are specified, reception is completed by the factor detected first.<br />

Make sure to configure the reception completion settings.<br />

1) Completed by a maximum data bit cycle<br />

To complete reception by detecting a maximum data bit cycle, you need to configure the RMCRCR2<br />

bits. If the falling edge of the data bit cycle isn’t monitored after time specified as<br />

threshold in the bits, a maximum data bit cycle is detected. The detection completes<br />

reception and generates an interrupt.<br />

2) Completed by excess low width<br />

To complete reception by detecting the low width, you need to configure the RMCRCR2<br />

bits. After the falling edge of the data bit is detected, if the signal stays low longer than<br />

specified, excess low width is detected. The detection completes reception and generates an<br />

interrupt.<br />

12.3.1.4 Enabling Reception<br />

By enabling the RMCREN bit after configuring the RMCRCR1, RMCRCR2 and<br />

RMCRCR3 registers, RMC is ready for reception. Detecting a leader initiates reception.<br />

(Note) Changing the configurations of the RMCRCR1, RMCRCR2 and RMCRCR3<br />

registers during reception may harm their proper operation. Be careful if you<br />

change them during reception.<br />

12.3.1.5 Reception<br />

Detecting a leader sets the RMCRSTAT bit. Simultaneously, a leader detection<br />

interrupt is generated if the RMCRCR2 bit is set. When the interrupt is generated, the<br />

RMCRSTAT bit is set.<br />

Next to the leader detection, each data bit is determined as 0 or 1. The results are stored in the<br />

RMCRBUF1, RMCRBUF 2 and RMCRBUF 3 registers up to 72bit. By setting “1” to the RMCRCR2<br />

bit, a remote control signal input falling edge interrupt can be generated in each falling<br />

edge of the data bit. When the interrupt is generated, the RMCRSTAT bit is set.<br />

Detecting the maximum data bit cycle or the excess low width completes reception and generates<br />

an interrupt.<br />

To check the status of RMC after reception is completed, read the Remote Control Receive Status<br />

Register.<br />

On completion of reception, RMC is waiting for the next leader.<br />

By setting RMC to receive a signal without a leader, RMC recognizes the received is data and starts<br />

reception without detecting a leader.<br />

If the next data reception is completed before reading the preceding received data, the preceding<br />

data is overwritten by the next one.<br />

RMC

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