TMPM330 - Keil

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(Step-5) Under development TMPM330 (rev 0.4)17-11 TMPM330 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection of that flash block. (TMPM330) Flash memory New application Program code [Reset procedure] (a) Mode judgment routine (b) Transfer routine (Step-6) Set RESET to “0” low to reset the TMPM330. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. (TMPM330) Flash memory New application program code [Reset procedure] (a) Mode judgment routine (b) Transfer routine (I/O) (Host) (c) Programming routine (I/O) RAM (Host) RAM New application program code (c) Programming routine 0 → 1 RESET Set to normal mode Flash Memory Operation
17.2.3 Single Boot Mode Under development TMPM330 (rev 0.4)17-12 TMPM330 In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMPM330 on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it. Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the TMPM330 is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMPM330 on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO0 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application’s password is checked before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. Flash Memory Operation
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1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
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Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
Page 267 and 268: 13.4 Description of Operations 13.4
Page 269 and 270: Under development TMPM330 (rev 0.4)
Page 271 and 272: Under development 3. Fixed channel
Page 273 and 274: 13.4.5 High-priority Conversion Mod
Page 275 and 276: Under development 14. Watchdog Time
Page 277 and 278: 14.3 Control Registers Under develo
Page 279 and 280: 14.4 Control Register Under develop
Page 281 and 282: 15.3 Control Register Under develop
Page 283 and 284: MINR Under development (2) Minute c
Page 285 and 286: DAYR DATER Under development (4) Da
Page 287 and 288: YEARR YEARR Under development (8) Y
Page 289 and 290: 15.5 Operational description (1) Re
Page 291 and 292: 3. Disabling the clock Under develo
Page 293 and 294: (2) 1Hz clock Under development TMP
Page 295 and 296: 16.1 Addresses [1] Port [1/4] ADR
Page 297 and 298: [1] Port 3/4] ADR Register name AD
Page 299 and 300: [2] 16-bit timer [1/4] ADR Registe
Page 301 and 302: [2] 16-bit timer [3/4] ADR Registe
Page 303 and 304: Under development [3] Serial bus in
Page 305 and 306: [5] 10-bit A/D converter (A/DC) ADR
Page 307 and 308: [10] Remote control signal preproce
Page 309 and 310: Under development JEDEC compliant f
Page 313 and 314: User Boot Mode Under development (1
Page 315 and 316: (Step-5) Under development TMPM330
Page 317: (Step-3) Under development TMPM330
Page 321 and 322: (Step-3) Under development TMPM330
Page 323 and 324: (1) Configuration for Single Boot M
Page 325 and 326: (5) Restrictions on internal memori
Page 327 and 328: Under development Table 17-7 Transf
Page 329 and 330: Under development Table 17-9 Transf
Page 331 and 332: (6) Operation of Boot Program Under
Page 335 and 336: Under development returns to the st
Page 337 and 338: Under development 3) Show Product I
Page 339 and 340: Under development 4) Chip Erase com
Page 341 and 342: 5) Acknowledge Responses Under deve
Page 343 and 344: Point A Point B Point C Point D Und
Page 345 and 346: Start Are all bytes the same? YES A
Page 347 and 348: (7) General Boot Program Flowchart
Page 349 and 350: (2) Basic operation Under developme
Page 357 and 358: Under development Table 17-17 Secur
Page 359 and 360: Address Normal comma nds Under deve
Page 361 and 362: (8) Flowchart Address = Address + 0
Page 363 and 364: 18. ROM protection 18.1 Outline Und
Page 365 and 366: 18.3 Register block. Under developm
Page 367: 18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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