TMPM330 - Keil

TBnIM
(0x4001_0xx8)
Under development
8.2.1.7 TMRB interrupt mask register (channels 0 through 9)
bit Symbol
TMRBn interrupt mask register (n=0~9)
31 30 29 28 27 26 25 24
Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
bit Symbol
Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
bit Symbol
Read/Write R R R R R R R R
After reset 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
bit Symbol TBIMOFn TBIMn1 TBIMn0
Read/Write R R
After reset 0 0 0 0
Function
“0” is read 1: Interrupt
TMPM330 (rev 0.4)8-14
is
masked
: Interrupt is masked if there is a match with timer register 0 (TBnRG0)
:Interrupt is masked if there is a match with timer register 1 (TBnRG1).
:Interrupt is masked if an up-and-down counter overflow occurs.
1:
Interrupt
is
masked
1:
Interrupt
is
masked
TMPM330
16-bit Timer/
Event Counters (TMRBs)