TMPM330 - Keil

Under development
(8) Data Reception at Logical Address Discrepancy
TMPM330 (rev0.4)11-21
TMPM330
By setting CECRCR1 , you can specify if data is received or not when destination
address does not correspond with the address set in the logical address register.
In this case, data is received as usual, and an interrupt is generated by detecting an error.
However, an ACK response of neither the header block nor the data block is sent.
(Note) A broadcast message is received regardless of the register setting.
(9) Start Bit Detection
Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the start
bit detection respectively.
is to specify the fastest start bit rising timing. is to specify the latest
start bit rising timing ((1) in the figure shown below).
is to specify the minimum cycle of a start bit. is to specify the
maximum cycle of a start bit ((2) in the figure shown below).
If a rising edge during the period (1) and a falling edge during the period (2) are detected, the start
bit is considered to be valid.
0ms
3.5ms-7cycle
3.5ms~
3.5ms 3.7ms 4.3ms 4.7ms
(1) (2)
3.7ms~
3.7ms+7cycle
4.3ms-7cycle
4.3ms~
4.7ms~
4.7ms+7cycle
CEC