TMPM330 - Keil

Under development
11.2.9 Receive Control Register 2 [CECRCR2]
bit Symbol
TMPM330 (rev0.4)11-9
TMPM330
15 14 13 12 11 10 9 8
― CEC
SWAV32
CEC
SWAV31
CEC
SWAV30
― CEC
SWAV22
CEC
SWAV21
Read/Write R R/W R R/W
After reset 0 0 0 0
Function
bit Symbol
:
:
:
:
“0” is
read.
Max. cycle to detect start bit
000: 4.7ms
001: 4.7ms+1cycle
010: 4.7ms+2cycles
011: 4.7ms+3cycles
100: 4.7ms+4cycles
101: 4.7ms+5cycles
110: 4.7ms+6cycles
111: 4.7ms+7cycles
“0” is
read.
Min. cycle to detect start bit
000: 4.3ms
001: 4.3ms-1cycle
010: 4.3ms-2cycles
011: 4.3ms-3cycles
100: 4.3ms-4cycles
101: 4.3ms-5cycles
110: 4.3ms-6cycles
111: 4.3ms-7cycles
CEC
SWAV20
7 6 5 4 3 2 1 0
― CEC
SWAV12
CEC
SWAV11
CEC
SWAV10
― CEC
SWAV02
CEC
SWAV01
CEC
SWAV00
Read/Write R R/W R R/W
After reset 0 0 0 0
“0” is Max. time of start bit rising timing. “0” is Min. time of start bit rising timing.
read. 000: 3.9ms
read. 000: 3.5ms
001: 3.9ms+1cycle
001: 3.5ms-1cycle
010: 3.9ms+2cycles
010: 3.5ms-2cycles
Function
011: 3.9ms+3cycles
011: 3.5ms-3cycles
100: 3.9ms+4cycles
100: 3.5ms-4cycles
101: 3.9ms+5cycles
101: 3.5ms-5cycles
110: 3.9ms+6cycles
110: 3.5ms-6cycles
111: 3.9ms+7cycles
111: 3.5ms-7cycles
Specifies the cycles to detect a start bit.
is for the maximum cycles. Enables to set it for each sampling clock
cycle between the ranges of 0 to +7 cycles from default value (4.7 ms).
is for the minimum cycles. Enables to set it for each sampling clock
cycle between the ranges of 0 to +7 cycles from default value (4.3 ms).
Specifies the rising timing of a start bit in its detection.
is for the maximum time of the rising timing. Enables to set it for each
sampling clock cycle between the ranges of 0 to +7 cycles from default value (3.9
ms).
is for the minimum time of the rising timing. Enables to set it for each
sampling clock cycle between the ranges of 0 to -7 cycles from default value (3.5
ms).
(Note) Changing the configurations during transmission or reception may harm its proper
operation. Before the change, set CECREN to disable the reception and read
the bit to ensure that the operation is stopped.
CEC