TMPM330 - Keil

Under development
TMPM330 (rev 0.4)17-43
TMPM330
predefined command write sequence, the flash memory will terminate the command execution
and return to the read mode.
(Note 1) Command sequences are executed from outside the flash memory area.
(Note 2) Each bus write cycle must be sequentially executed by 32-bit data transmit command.
While a command sequence is being executed, access to the flash memory is prohibited.
Also, don't generate any interrupt (except debug exceptions when a DSU probe is
connected).If such an operation is made, it can result in an unexpected read access to the
flash memory and the command sequencer may not be able to correctly recognize the
command. While it could cause an abnormal termination of the command sequence, it is
also possible that the written command is incorrectly recognized.
(Note 3) For the command sequencer to recognize a command, the device must be in the read
mode prior to executing the command. Be sure to check before the first bus write cycle that
the FLCS RDY/BSY bit is set to "1." It is recommended to subsequently execute a Read
command.
(Note 4) Upon issuing a command, if any address or data is incorrectly written, be sure to perform a
software reset to return to the read mode again.
(3) Reset
Hardware reset
A hardware reset is used to cancel the operational mode set by the command write
operation when forcibly termination during auto programming/ erasing or abnormal
termination during auto operations occurs. The flash memory has a reset input as the
memory block and it is connected to the CPU reset signal. Therefore, when the RESET
input pin of this device is set to VIL or when the CPU is reset due to any overflow of the
watch dog timer, the flash memory will return to the read mode terminating any automatic
operation that may be in progress. It should also be noted that applying a hardware reset
during an automatic operation can result in incorrect rewriting of data. In such a case, be
sure to perform the rewriting again.
Refer to Section 17.2.1 "Reset Operation" for CPU reset operations. After a given reset
input, the CPU will read the reset vector data from the flash memory and starts operation
after the reset is removed.
Flash Memory Operation