TMPM330 - Keil

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[7] Real time clock (RTC) ADR Register name ADR Register name Under development ADR TMPM330 (rev.0.4) 16-13 Register name ADR 0x4004_0100 SECR 0x4004_0110 0x4004_0120 0x4004_0130 0x4004_0101 MINR 0x4004_0111 0x4004_0121 0x4004_0131 0x4004_0102 HOURR 0x4004_0112 0x4004_0122 0x4004_0132 0x4004_0103 0x4004_0113 0x4004_0123 0x4004_0133 0x4004_0104 DAYR 0x4004_0114 0x4004_0124 0x4004_0134 0x4004_0105 DATER 0x4004_0115 0x4004_0125 0x4004_0135 0x4004_0106 MONTHR 0x4004_0116 0x4004_0126 0x4004_0136 0x4004_0107 YEARR 0x4004_0117 0x4004_0127 0x4004_0137 0x4004_0108 PAGER 0x4004_0118 0x4004_0128 0x4004_0138 0x4004_0109 0x4004_0119 0x4004_0129 0x4004_0139 0x4004_010A 0x4004_011A 0x4004_012A 0x4004_013A 0x4004_010B 0x4004_011B 0x4004_012B 0x4004_013B 0x4004_010C RESTR 0x4004_011C 0x4004_012C 0x4004_013C 0x4004_010D 0x4004_011D 0x4004_012D 0x4004_013D 0x4004_010E 0x4004_011E 0x4004_012E 0x4004_013E 0x4004_010F 0x4004_011F 0x4004_012F 0x4004_013F [8] Clock generator (CG) ADR Register name ADR Register name ADR Register name ADR TMPM330 Register name Register name 0x4004_0200 SYSCR0 0x4004_0210 CKSEL 0x4004_0220 IMCGA0 0x4004_0230 0x4004_0201 SYSCR1 0x4004_0211 0x4004_0221 IMCGA1 0x4004_0231 0x4004_0202 SYSCR2 0x4004_0212 0x4004_0222 IMCGA2 0x4004_0232 0x4004_0203 0x4004_0213 0x4004_0223 IMCGA3 0x4004_0233 0x4004_0204 OSCCR0 0x4004_0214 ICRCG 0x4004_0224 IMCGB0 0x4004_0234 0x4004_0205 OSCCR1 0x4004_0215 0x4004_0225 IMCGB1 0x4004_0235 0x4004_0206 0x4004_0216 0x4004_0226 IMCGB2 0x4004_0236 0x4004_0207 0x4004_0217 0x4004_0227 IMCGB3 0x4004_0237 0x4004_0208 STBYCR0 0x4004_0218 NMIFLG 0x4004_0228 IMCGC0 0x4004_0238 0x4004_0209 STBYCR1 0x4004_0219 0x4004_0229 IMCGC1 0x4004_0239 0x4004_020A STBYCR2 0x4004_021A 0x4004_022A IMCGC2 0x4004_023A 0x4004_020B 0x4004_021B 0x4004_022B IMCGC3 0x4004_023B 0x4004_020C PLLSEL 0x4004_021C RSTFLG 0x4004_022C IMCGD0 0x4004_023C 0x4004_020D 0x4004_021D 0x4004_022D 0x4004_023D 0x4004_020E 0x4004_021E 0x4004_022E 0x4004_023E 0x4004_020F 0x4004_021F 0x4004_022F 0x4004_023F [9] CEC ADR Register name ADR Register name ADR Register name ADR Register name 0x4004_0300 CECEN 0x4004_0310 CECRBUF 0x4004_0320 CECTEN 0x4004_0330 CECTSTAT 0x4004_0301 0x4004_0311 “ 0x4004_0321 0x4004_0331 0x4004_0302 0x4004_0312 0x4004_0322 0x4004_0332 0x4004_0303 0x4004_0313 0x4004_0323 0x4004_0333 0x4004_0304 CECADD 0x4004_0314 CECRCR1 0x4004_0324 CECTBUF 0x4004_0334 0x4004_0305 “ 0x4004_0315 “ 0x4004_0325 “ 0x4004_0335 0x4004_0306 0x4004_0316 “ 0x4004_0326 0x4004_0336 0x4004_0307 0x4004_0317 “ 0x4004_0327 0x4004_0337 0x4004_0308 CECRESET 0x4004_0318 CECRCR2 0x4004_0328 CECTCR 0x4004_0338 0x4004_0309 0x4004_0319 “ 0x4004_0329 “ 0x4004_0339 0x4004_030A 0x4004_031A 0x4004_032A “ 0x4004_033A 0x4004_030B 0x4004_031B 0x4004_032B 0x4004_033B 0x4004_030C CECREN 0x4004_031C CECRCR3 0x4004_032C CECRSTAT 0x4004_033C 0x4004_030D 0x4004_031D “ 0x4004_032D 0x4004_033D 0x4004_030E 0x4004_031E “ 0x4004_032E 0x4004_033E 0x4004_030F 0x4004_031F 0x4004_032F 0x4004_033F Table of Special Function Registers
[10] Remote control signal preprocessor (RMC) ADR Register name ADR Register name Under development ADR TMPM330 (rev.0.4) 16-14 Register name ADR 0x4004_0400 RMC0EN 0x4004_0410 RMC0RBUF3 0x4004_0420 RMC0RCR4 0x4004_0430 0x4004_0401 0x4004_0411 0x4004_0421 0x4004_0431 0x4004_0402 0x4004_0412 0x4004_0422 0x4004_0432 0x4004_0403 0x4004_0413 0x4004_0423 0x4004_0433 0x4004_0404 RMC0REN 0x4004_0414 RMC0RCR1 0x4004_0424 RMC0RSTAT 0x4004_0434 0x4004_0405 0x4004_0415 “ 0x4004_0425 “ 0x4004_0435 0x4004_0406 0x4004_0416 “ 0x4004_0426 0x4004_0436 0x4004_0407 0x4004_0417 “ 0x4004_0427 0x4004_0437 0x4004_0408 RMC0RBUF1 0x4004_0418 RMC0RCR2 0x4004_0428 0x4004_0438 0x4004_0409 “ 0x4004_0419 “ 0x4004_0429 0x4004_0439 0x4004_040A “ 0x4004_041A “ 0x4004_042A 0x4004_043A 0x4004_040B “ 0x4004_041B “ 0x4004_042B 0x4004_043B 0x4004_040C RMC0RBUF2 0x4004_041C RMC0RCR3 0x4004_042C 0x4004_043C 0x4004_040D “ 0x4004_041D “ 0x4004_042D 0x4004_043D 0x4004_040E “ 0x4004_041E 0x4004_042E 0x4004_043E 0x4004_040F “ 0x4004_041F 0x4004_042F 0x4004_043F ADR Register name ADR Register name ADR Register name ADR 0x4004_0440 RMC1EN 0x4004_0450 RMC1RBUF3 0x4004_0460 RMC1RCR4 0x4004_0470 0x4004_0441 0x4004_0451 0x4004_0461 0x4004_0471 0x4004_0442 0x4004_0452 0x4004_0462 0x4004_0472 0x4004_0443 0x4004_0453 0x4004_0463 0x4004_0473 0x4004_0444 RMC1REN 0x4004_0454 RMC1RCR1 0x4004_0464 RMC1RSTAT 0x4004_0474 0x4004_0445 0x4004_0455 “ 0x4004_0465 “ 0x4004_0475 0x4004_0446 0x4004_0456 “ 0x4004_0466 0x4004_0476 0x4004_0447 0x4004_0457 “ 0x4004_0467 0x4004_0477 0x4004_0448 RMC1RBUF1 0x4004_0458 RMC1RCR2 0x4004_0468 0x4004_0478 0x4004_0449 “ 0x4004_0459 “ 0x4004_0469 0x4004_0479 0x4004_044A “ 0x4004_045A “ 0x4004_046A 0x4004_047A 0x4004_044B “ 0x4004_045B “ 0x4004_046B 0x4004_047B 0x4004_044C RMC1RBUF2 0x4004_045C RMC1RCR3 0x4004_046C 0x4004_047C 0x4004_044D “ 0x4004_045D “ 0x4004_046D 0x4004_047D 0x4004_044E “ 0x4004_045E 0x4004_046E 0x4004_047E 0x4004_044F “ 0x4004_045F 0x4004_046F 0x4004_047F [11]Flash ADR Register name ADR Register name ADR Register name ADR 0x4004_0500 SECBIT 0x4004_0510 0x4004_0520 FLCS 0x4004_0530 0x4004_0501 “ 0x4004_0511 0x4004_0521 “ 0x4004_0531 0x4004_0502 “ 0x4004_0512 0x4004_0522 “ 0x4004_0532 0x4004_0503 “ 0x4004_0513 0x4004_0523 “ 0x4004_0533 0x4004_0504 0x4004_0514 0x4004_0524 0x4004_0534 0x4004_0505 0x4004_0515 0x4004_0525 0x4004_0535 0x4004_0506 0x4004_0516 0x4004_0526 0x4004_0536 0x4004_0507 0x4004_0517 0x4004_0527 0x4004_0537 0x4004_0508 0x4004_0518 0x4004_0528 0x4004_0538 0x4004_0509 0x4004_0519 0x4004_0529 0x4004_0539 0x4004_050A 0x4004_051A 0x4004_052A 0x4004_053A 0x4004_050B 0x4004_051B 0x4004_052B 0x4004_053B 0x4004_050C 0x4004_051C 0x4004_052C 0x4004_053C 0x4004_050D 0x4004_051D 0x4004_052D 0x4004_053D 0x4004_050E 0x4004_051E 0x4004_052E 0x4004_053E 0x4004_050F 0x4004_051F 0x4004_052F 0x4004_053F TMPM330 Register name Register name Register name Table of Special Function Registers
Page 1 and 2:
1. Overview and Features Under deve
Page 3 and 4:
Under development (13) Standby mode
Page 5 and 6:
2. Pin Layout and Pin Functions Und
Page 7 and 8:
Pin No. Under development Table 2.1
Page 9 and 10:
Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Page 123 and 124:
Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Page 165 and 166:
Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
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Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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Page 235 and 236:
(Note) Under development When you c
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Page 239 and 240:
Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
Page 255 and 256: ADMOD1 Under development A/D Mode C
Page 261 and 262: ADREG2AL ADREG2AH ADREG3BL ADREG3BH
Page 263 and 264: ADREG6EL ADREG6EL ADREG6EL ADREG6EL
Page 265 and 266: ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
Page 267 and 268: 13.4 Description of Operations 13.4
Page 269 and 270: Under development TMPM330 (rev 0.4)
Page 271 and 272: Under development 3. Fixed channel
Page 273 and 274: 13.4.5 High-priority Conversion Mod
Page 275 and 276: Under development 14. Watchdog Time
Page 277 and 278: 14.3 Control Registers Under develo
Page 279 and 280: 14.4 Control Register Under develop
Page 281 and 282: 15.3 Control Register Under develop
Page 283 and 284: MINR Under development (2) Minute c
Page 285 and 286: DAYR DATER Under development (4) Da
Page 287 and 288: YEARR YEARR Under development (8) Y
Page 289 and 290: 15.5 Operational description (1) Re
Page 291 and 292: 3. Disabling the clock Under develo
Page 293 and 294: (2) 1Hz clock Under development TMP
Page 295 and 296: 16.1 Addresses [1] Port [1/4] ADR
Page 297 and 298: [1] Port 3/4] ADR Register name AD
Page 299 and 300: [2] 16-bit timer [1/4] ADR Registe
Page 301 and 302: [2] 16-bit timer [3/4] ADR Registe
Page 303 and 304: Under development [3] Serial bus in
Page 305: [5] 10-bit A/D converter (A/DC) ADR
Page 309 and 310: Under development JEDEC compliant f
Page 313 and 314: User Boot Mode Under development (1
Page 315 and 316: (Step-5) Under development TMPM330
Page 319 and 320: 17.2.3 Single Boot Mode Under devel
Page 323 and 324: (1) Configuration for Single Boot M
Page 325 and 326: (5) Restrictions on internal memori
Page 327 and 328: Under development Table 17-7 Transf
Page 329 and 330: Under development Table 17-9 Transf
Page 331 and 332: (6) Operation of Boot Program Under
Page 335 and 336: Under development returns to the st
Page 337 and 338: Under development 3) Show Product I
Page 339 and 340: Under development 4) Chip Erase com
Page 341 and 342: 5) Acknowledge Responses Under deve
Page 343 and 344: Point A Point B Point C Point D Und
Page 345 and 346: Start Are all bytes the same? YES A
Page 347 and 348: (7) General Boot Program Flowchart
Page 349 and 350: (2) Basic operation Under developme
Page 357 and 358:
Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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