TMPM330 - Keil

12.3 Operation Description
Under development
12.3.1 Reception of Remote Control Signal
12.3.1.1 Sampling Clock
A remote control signal is sampled by low-speed clock (fs).
12.3.1.2 Basic Operation
TMPM330 (rev0.4)12-12
TMPM330
RMC starts to receive a data bit if a leader is detected while RMC is waiting for a leader. Based on a
falling edge cycle, the data bit is determined as 0 or 1. By detecting a leader while RMC is waiting for
a leader, a leader detection interrupt is generated, and the data bit reception starts. The data bit is
determined as 0 or 1 based on a falling edge cycle. RMC is capable of receiving data up to 72bit.
Reception is completed by detecting either a maximum data bit cycle or the excess low width. On
completion of reception, RMC is waiting for the next leader, and the Remote Control Receive Data
Buffer Registers and the Remote Control Receive Status Register are updated.
Data reception completed by detecting the max data bit cycle
Waiting for
leader
Detecting leader
Capable of receiving
data up to 72bit
Maximum data bit cycle interrupt
Waiting for
leader
Specified period of a maximum
data bit cycle
RMC