TMPM330 - Keil

9.3.6 Receive FIFO Buffer
Under development
TMPM330 (rev 0.4) 9-16
TMPM330
In addition to the double buffer function already described, data may be stored using the
receive FIFO buffer. By setting of the SC0FCNF register and of the
SC0MOD1 register, the 4-byte receive buffer can be enabled. Also, in the UART mode or
I/O interface mode, data may be stored up to a predefined fill level. When the receive FIFO
buffer is to be used, be sure to enable the double buffer function.
If data with parity bit is to be received in the UART mode, parity check must be performed
each time a data frame is received.
9.3.7 Receive FIFO Operation
I/O interface mode with SCLK output:
The following example describes the case a 4-byte data stream is received in the half duplex
mode:
SC0RFC=01: Clears receive FIFO and sets the condition of interrupt generation.
SC0RFC=00: Sets the interrupt to be generated at fill level 4.
SC0FCNF =10111: Automatically inhibits continued reception after reaching the fill level.
The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill
level.
In this condition, 4-byte data reception may be initiated by setting the half duplex transmission
mode and writing “1” to the RXE bit. After receiving 4 bytes, the RXE bit is automatically
cleared and the receive operation is stopped (SCLK is stopped).
Receive buffer 1
Receive buffer 2
RX FIFO
RBFLL
Receive interrupt
RXE
1 byte
2 byte
1 byte
1 byte
3 byte
2 byte
Fig. 9-3 Receive FIFO Operation
4 byte
3 byte
2 byte 3 byte
1 byte 2 byte
1 byte
4 byte
4 byte
3 byte
2 byte
1 byte
Serial Channel (SIO)