TMPM330 - Keil

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Under development (8) Data Reception at Logical Address Discrepancy TMPM330 (rev0.4)11-21 TMPM330 By setting CECRCR1 , you can specify if data is received or not when destination address does not correspond with the address set in the logical address register. In this case, data is received as usual, and an interrupt is generated by detecting an error. However, an ACK response of neither the header block nor the data block is sent. (Note) A broadcast message is received regardless of the register setting. (9) Start Bit Detection Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the start bit detection respectively. is to specify the fastest start bit rising timing. is to specify the latest start bit rising timing ((1) in the figure shown below). is to specify the minimum cycle of a start bit. is to specify the maximum cycle of a start bit ((2) in the figure shown below). If a rising edge during the period (1) and a falling edge during the period (2) are detected, the start bit is considered to be valid. 0ms 3.5ms-7cycle 3.5ms~ 3.5ms 3.7ms 4.3ms 4.7ms (1) (2) 3.7ms~ 3.7ms+7cycle 4.3ms-7cycle 4.3ms~ 4.7ms~ 4.7ms+7cycle CEC
(10) Waveform Error Detection Under development TMPM330 (rev0.4)11-22 TMPM330 To detect an error when a received waveform is out of the defined tolerance range, configure the CECRCR3 register. An error is detected when the bit of the CECRCR3 register is enabled. You can specify the detection time in the bits. If the rising edge is detected during the period (1) or (2) shown below, or not detected in the timing described in (3), a waveform error interrupt is generated. (1) A period between the beginning of a bit and the fastest logical “1” rising timing. (2) A period between the latest logical “1” rising timing and the fastest logical “0” rising timing. (3) The latest logical “0” rising timing. Error detection period 0ms 0.4ms-7cycle ~0.4ms 0.4ms 0.8ms 1.3ms 1.7ms (1) (2) (3) 0.8ms~ 0.8ms+7cycle 1.3ms-7cycle ~1.3ms 1.7ms~ 1.7ms+7cycle CEC
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1. Overview and Features Under deve
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Under development (13) Standby mode
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2. Pin Layout and Pin Functions Und
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Pin No. Under development Table 2.1
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Type Function Function/ BOOT Functi
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Type Function/ Debug Function # of
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2.3 Pin Names and Power Supply Pins
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4. Memory map 4.1 Memory map 0x4008
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0x4008 FFFF 0x4000 0000 0x2000 1FFF
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X1 X2 XT1 XT2 5.2.2 Clock System Bl
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SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
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STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
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CKSEL 5.3.2.5 System Clock Selectio
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5.4.2 Main System Clock External os
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5.4.4 System Clock Pin Output Funct
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5.8.1 IDLE Mode Under development T
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Under development 5.8.4 Low power C
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5.8.7 Warm-up Under development TMP
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Under development 5.8.8.3 Transitio
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6.2.2 Generation Under development
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Under development Table 6-1 List of
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Under development TMPM330 (rev0.4)
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6.3.6 Interrupt Service Routine Und
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6.4.2 CG Interrupt Mode Control Reg
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6.4.4 CG Interrupt Mode Control Reg
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6.4.7 NMI Flag Register Under devel
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7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Page 165 and 166: Under development Table 10-1 Base C
Page 167 and 168: SBIxBR0 bit Symbol I2SBI0 Under dev
Page 169 and 170: 10.5 Control in the I 2 C Bus Mode
Page 171 and 172: Under development 10.5.6 Configurin
Page 173 and 174: Master A Master B Under development
Page 175 and 176: Under development 10.6 Data Transfe
Page 177 and 178: SCL pin Write to SBIxDBR SDA pin I
Page 179 and 180: Slave mode ( = “0”) Under devel
Page 181 and 182: 10.6.4 Generating the Stop Conditio
Page 183 and 184: Under development 10.7 Control in t
Page 185 and 186: SBIxDBR SBIxCR2 Under development S
Page 187 and 188: 10.7.1 Serial Clock SCK pin output
Page 189 and 190: 10.7.2 Transfer Modes Under develop
Page 191 and 192: SCK pin SIOF SO pin bit 6 Under dev
Page 193 and 194: SCK pin (output) SO pin SI pin IN
Page 195 and 196: 11.2 Registers 11.2.1 Control Regis
Page 197 and 198: Under development 11.2.5 Software R
Page 199 and 200: Under development 11.2.7 Receive Bu
Page 201 and 202: Under development TMPM330 (rev0.4)1
Page 203 and 204: Under development 11.2.10 Receive C
Page 205 and 206: Under development 11.2.11 Transmit
Page 207 and 208: Under development 11.2.13 Transmit
Page 209 and 210: Under development 11.2.14 Receive I
Page 211 and 212: 11.3 Operations 11.3.1 Reception 11
Page 213: (3) Cycle Error Under development C
Page 217 and 218: 11.3.1.6 Data Sampling Point Under
Page 219 and 220: 11.3.1.8 Detecting Error Interrupt
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Page 223 and 224: 11.3.2.2 Preconfiguration Under dev
Page 225 and 226: 11.3.2.3 Starting Transmission Unde
Page 227 and 228: (2) ACK error Under development TMP
Page 229 and 230: Under development 12 Remote control
Page 231 and 232: Under development 12.2.2 Remote Con
Page 235 and 236: (Note) Under development When you c
Page 239 and 240: Under development 12.2.11 Remote Co
Page 241 and 242: 12.3.1.3 Preparation Under developm
Page 243 and 244: (3) Settings of Data Bit Determinat
Page 245 and 246: 12.3.1.6 Reception Completion Under
Page 247 and 248: Under development 12.3.1.8 Receivin
Page 249 and 250: Remote control signal waveform (inp
Page 251 and 252: Remote control signal in phase meth
Page 253 and 254: 13.1 Registers Under development Th
Page 255 and 256: ADMOD1 Under development A/D Mode C
Page 261 and 262: ADREG2AL ADREG2AH ADREG3BL ADREG3BH
Page 263 and 264: ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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