TMPM330 - Keil

Under development
TMPM330 (rev0.4)11-28
TMPM330
The information that the interrupts are suspended is held until the EOM bit is received or the
timeout occurs. Thus, an interrupt is generated in each reception of a byte of data if multiple bytes
are received while interrupts are suspended. “1” is set to the bits of the CECRSTAT register: the
bit that indicates the reception completion, and the bits corresponding to the detected
errors. The flags of the suspended interrupts and the reception completion are set to the bits of the
CECRSTAT register.
(Note 1) A minimum cycle error interrupt is generated upon detecting a minimum cycle
error in the next received bit while interrupts are suspended. “0” is output to CEC
for approx. 3.6 ms.
The flags of the suspended interrupts and the minimum cycle error are set to the
bits of the CECRSTAT register.
(Note 2) If an interrupt other than a minimum cycle error interrupt is generated while
interrupts are suspended, CEC continues reception by the ACK response or the
timeout.
All the flags of the detected interrupts are set to the bits of the CECRSTAT register.
11.3.1.10 Stopping Reception
Writing “0” to the CECREN bit disables data reception. The reception is stopped upon
disabling the bit during reception. The received data is discarded.
(Note) If the reception is disabled while “0” is sent as a signal of minimum cycle error, the
“0” output is stopped as well.
CEC