TMPM330 - Keil

11.3.1.4 Enabling Reception
Under development
TMPM330 (rev0.4)11-23
TMPM330
After configuring the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers, CEC is ready for
reception by enabling the CECREN bit. Detecting a start bit initiates the reception.
(Note) Changing the configurations of the CECADD, CECRCR1, CECRCR2 and CECRCR3
registers during transmission or reception may harm its proper operation. Before
the change of the registers shown below, set the CECREN bit to
disable the reception and read the bit and the CECTEN bit
to ensure that the operation is stopped.
CECRCR1
Noise cancellation time
Time to identify cycle error
Data reception at logical address
discrepancy
CECRCR2
CECRCR3
11.3.1.5 Reception
Start bit detection
Waveform error detection (when
enabled)
After detecting a start bit, a start bit interrupt is generated, and the CECRSTAT bit is
set.
Upon receiving a byte of data, the EOM and ACK bits, they are stored in the CECRBUF register. A
receive interrupt is generated and it causes the CECRSTAT bit to be set. Same as the
other data, the ACK bit that monitored the CEC line is stored instead of the one generated in the
CEC circuit.
The reception continues from the first data block until the final data block that has the EOM bit
indicating “1”. After detecting the final data block, CEC waits for a next start bit.
CEC