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TMPM330 - Keil

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6.4.3 CG Interrupt Mode Control Register B<br />

Under development<br />

<strong>TMPM330</strong> (rev0.4) 6-13<br />

<strong>TMPM330</strong><br />

7 6 5 4 3 2 1 0<br />

IMCGB bit Symbol EMCG42 EMCG41 EMCG40 EMST41 EMST40 INT4EN<br />

Read/Write R R/W R R R/W<br />

After reset 0 0 1 0 0 0 0 0<br />

Function<br />

“0” is read. Active state setting of INT4 standby<br />

clear request (101~111: setting<br />

prohibited)<br />

000: “L” level<br />

001: “H” level<br />

010: Falling edge<br />

011: Rising edge<br />

100: Both edges<br />

Active state of INT4<br />

standby clear request<br />

00: -<br />

01: Rising edge<br />

10: Falling edge<br />

11: Both edges<br />

“0” is read. INT4 clear<br />

input<br />

0: Disable<br />

1: Enable<br />

15 14 13 12 11 10 9 8<br />

bit Symbol EMCG52 EMCG51 EMCG50 EMST51 EMST50 INT5EN<br />

Read/Write R R/W R R R/W<br />

After reset 0 0 1 0 0 0 0 0<br />

Function “0” is read. Active state setting of INT5 standby<br />

clear request. (101~111: setting<br />

prohibited)<br />

Active state of INT5<br />

standby clear request<br />

“0” is read. INT5 clear<br />

input<br />

000: “L” level<br />

001: “H” level<br />

010: Falling edge<br />

011: Rising edge<br />

100: Both edges<br />

00: -<br />

01: Rising edge<br />

10: Falling edge<br />

11: Both edges<br />

0: Disable<br />

1: Enable<br />

23 22 21 20 19 18 17 16<br />

bit Symbol EMCG62 EMCG61 EMCG60 EMST61 EMST60 INT6EN<br />

Read/Write R R/W R R R/W<br />

After reset 0 0 1 0 0 0 0 0<br />

Function “0” is read. Active state setting of INTCECRX<br />

standby clear request.<br />

Active state of<br />

INTCECRX<br />

“0” is read. INTCEC<br />

RX Clear<br />

standby clear request<br />

input<br />

Set it as shown below.<br />

011: Rising edge<br />

00: -<br />

01: Rising edge<br />

10: Falling edge<br />

11: Both edges<br />

0: Disable<br />

1: Enable<br />

31 30 29 28 27 26 25 24<br />

bit Symbol EMCG72 EMCG71 EMCG70 EMST71 EMST70 INT7EN<br />

Read/Write R R/W R R R/W<br />

After reset 0 0 1 0 0 0 0 0<br />

Function “0” is read. Active state setting of INTRMCRX0<br />

standby clear request.<br />

Active state of<br />

INTRMCRX0 standby<br />

“0” is read. INTRMC<br />

RX0 Clear<br />

clear request<br />

input<br />

Set it as shown below.<br />

011: Rising edge<br />

00: -<br />

01: Rising edge<br />

10: Falling edge<br />

11: Both edges<br />

0: Disable<br />

1: Enable<br />

(Note 1) Refer to EMSTxx bit to know the active condition which is used for clearing<br />

standby.<br />

(Note 2) Please specify the bit for the edge first and then specify the bit for the<br />

. Setting them simultaneously is prohibited.<br />

Interrupts

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