TMPM330 - Keil

14.2 Watchdog Timer Interrupt
Under development
TMPM330 (rev 0.4) 14-2
TMPM330
The watchdog timer consists of the binary counters that are arranged in 26 stages and work using the
fSYS/2 system clock as an input clock. The outputs produced by these binary counters are 2 16 , 2 18 , 2 20 ,
2 22 , 2 24 are 2 26 .By selecting one of these outputs with WDMOD , a watchdog timer
interrupt can be generated and the WDTOUT is output when an overflow occurs, as shown in Fig.
14-2.
Because the watchdog timer interrupt is a non-maskable interrupt factor, NMIFLG at the
INTC performs a task of identifying it.
The output pin of the watchdog timer can reset the peripherals by outputting “0” caused by an
overflow. The output is set to “1”if the watchdog timer is cleared (if the clear code 4EH is written to the
WDCR register). The WDTOUT pin outputs “0” at normal mode unless the clear code is written to
WDCR register.
WDT counter
WDT interrupt
WDT clear
WDTOUT
Fig. 14-2 Normal Mode
When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a reset is
affected for a 32-state time, as shown in Fig. 14-3. If this reset is affected, the clock fSYS that the clock
gear generates by dividing the clock fC of the high-speed oscillator by 1 is used as an input clock fSYS.
WDT counter
WDT interrupt
Internal reset
WDTOUT
n Overflow
n
Overflow
Fig. 14-3 Reset Mode
Write of a clear code
32-state
(3.2 μs @ fosc = 10 MHz, fC = fsys = 10 MHz,)
0
Watchdog Timer