TMPM330 - Keil

Under development
11.2.13 Transmit Control Register [CECTCR]
TMPM330 (rev0.4)11-14
TMPM330
23 22 21 20 19 18 17 16
bit Symbol ― CECSTRS
2
CECSTRS
1
CECSTRS
0
― CECSPRD
2
CECSPRD
1
Read/Write R R/W R R/W
After reset 0 0 0 0
“0” is Rising timing of start bit
“0” is Start bit cycle
read.
read.
000: Reference value (RV)
000: RV
001: RV –1cycle
001: RV –1cycle
Function
010: RV –2cycle
011: RV –3cycle
010: RV –2cycle
011: RV –3cycle
100: RV –4cycle
100: RV –4cycle
101: RV –5cycle
101: RV –5cycle
110: RV –6cycle
110: RV –6cycle
111: RV –7cycle
111: RV –7cycle
CECSPRD
0
15 14 13 12 11 10 9 8
bit Symbol ― CECDTRS
2
CECDTRS
1
CECDTRS
0
CECDPRD
3
CECDPRD
2
CECDPRD
1
CECDPRD
0
Read/Write R R/W R/W
After reset 0 0 0
“0” is Rising timing of data bit
Data bit cycle
read. 000: RV
0000: RV
1000: RV –8cycle
001: RV –1cycle
0001: RV –1cycle 1001: RV –9cycle
010: RV –2cycle
0010: RV –2cycle 1010: RV –10cycle
Function
011: RV –3cycle
0011: RV –3cycle 1011: RV –11cycle
100: RV –4cycle
0100: RV –4cycle 1100: RV –12cycle
101: RV –5cycle
0101: RV –5cycle 1101: RV –13cycle
110: RV –6cycle
0110: RV –6cycle 1110: RV –14cycle
111: RV –7cycle
0111: RV –7cycle 1111: RV –15cycle
7 6 5 4 3 2 1 0
bit Symbol ― CECBRD CECFREE
3
CECFREE
2
CECFREE
1
CECFREE
0
Read/Write R R/W R/W
After reset 0 0 0
“0” is read. Broadcast Time of bus to be free
transmissi 0000: 1 bit cycle 1000: 9 bit cycle
on 0001: 2 bit cycle 1001: 10 bit cycle
0010: 3 bit cycle 1010: 11 bit cycle
Function
0: No 0011: 4 bit cycle 1011: 12 bit cycle
1: Yes 0100: 5 bit cycle 1100: 13 bit cycle
0101: 6 bit cycle 1101: 14 bit cycle
0110: 7 bit cycle 1110: 15 bit cycle
0111: 8 bit cycle 1111: 16 bit cycle
CEC