TMPM330 - Keil

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1.2 Block Diagram Cortex-M3 CPU Debug NVIC Under development Bus Bridge CG PORT 0~A SIO (3ch) I2C (3ch) CEC Remote control signal preprocessor (2ch) I-Code D-Code System AHB-Bus-Matrix IO-Bus I/F I/F I/F Fig. 1.1 TMPM330 Block Diagram TMPM330 (rev0.4) 1-5 FLASH RAM BOOT ROM TMRB (10ch) WDT RTC ADC (12ch) TMPM330 Overview and Features
2. Pin Layout and Pin Functions Under development This chapter describes the pin layout, pin names and pin functions of TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG. 2.1 Pin Layout (Top view) Fig. 2-1 shows the pin layout of TMPM330FDFG/TMPM330FYFG/TMPM330FWF. AN10/ PD6 AN11/ PD7 AVSS VREFH AVCC INT4/ PG3 TB9OUT/ PK2 TB7OUT/ PJ5 TB2IN0/ PH4 TB2IN1/ PH5 TB8OUT/ PG7 TEST2 DVSS DVCC SDA2/ SO2/ PG4 SCL2/ SI2/ PG5 SCK2/ PG6 TEST1 INT5/ PF7 TXD0/ PE0 RXD0/ PE1 SCLK0/ PE2 TXD1/ PE4 RXD1/ PE5 SCLK1/ PE6 5 10 15 20 25 PD5 /AN9 PD4 /AN8 PD3 /AN7 PD2 /AN6 PD1 /AN5 PD0 /AN4 PC3 /AN3 PC2 /AN2 PC1 /AN1 PC0 /AN0 TEST4 PE3 /RXIN0 PJ4 /TB6OUT PJ3 /INT3 PJ2 /INT2 PH7 /TB3IN1 PH6 /TB3IN0 PI7 /TB4IN1 RESET MODE NMI PI6 /TB4IN0 XT2 XT1 REGVCC 100 30 95 TMPM330FDFG TMPM330FYFG TMPM330FWFG 35 90 Top View 40 85 SDA0/ SO0/ PG0 SCL0/ SI0/ PG1 SCK0/ PG2 PB3 BOOT/ TB0IN0/ PH0 TB0IN1/ PH1 TB1IN0/ PH0 TXD2/ PF0 RXD2/ PF1 SCLK2/ PF2 TB1IN1/ PH3 PB4 TB0OUT/ PI1 INT6/ PJ6 TB1OUT/ PI1 PB5 TB2OUT/ PI2 PB6 SDA1/ SO1/ PF4 SCL1/ SI1/ PF5 SCK1/ PF6 PB7 TB3OUT/ PI3 INT1/ PJ1 CEC/ PK0 Fig. 2.1 Pin Layout (LQFP100) TMPM330 (rev0.4) 2-1 45 80 50 75 70 65 60 55 TMPM330 REGVSS X1 CVSS X2 CVCC PJ0 /INT0 PA7 PA6 /TRACEDATA3 PA5 /TRACEDATA2 PA4 /TRACEDATA1 PA3 /TRACEDATA0 PA2 /TRACECLK DVSS DVCC PF3 /RXIN1 PB2 / TRST PB1 /TDI PJ7 /INT7 TEST3 PA1 /TCK /SWCLK PA0 /TMS /SWDIO PB0 /TDO /SWV PI5 /TB5OUT PI4 /TB4OUT PK1 /SCOUT Pin Layout and Pin Functions
Page 1 and 2: 1. Overview and Features Under deve
Page 3: Under development (13) Standby mode
Page 7 and 8: Pin No. Under development Table 2.1
Page 9 and 10: Type Function Function/ BOOT Functi
Page 11 and 12: Type Function/ Debug Function # of
Page 13 and 14: 2.3 Pin Names and Power Supply Pins
Page 15 and 16: 4. Memory map 4.1 Memory map 0x4008
Page 17 and 18: 0x4008 FFFF 0x4000 0000 0x2000 1FFF
Page 19 and 20: X1 X2 XT1 XT2 5.2.2 Clock System Bl
Page 21 and 22: SYSCR0 SYSCR1 SYSCR2 5.3.2 Detailed
Page 23 and 24: STBYCR0 STBYCR1 STBYCR2 5.3.2.3 Sta
Page 25 and 26: CKSEL 5.3.2.5 System Clock Selectio
Page 27 and 28: 5.4.2 Main System Clock External os
Page 29 and 30: 5.4.4 System Clock Pin Output Funct
Page 31 and 32: 5.8.1 IDLE Mode Under development T
Page 33 and 34: Under development 5.8.4 Low power C
Page 35 and 36: 5.8.7 Warm-up Under development TMP
Page 37 and 38: Under development 5.8.8.3 Transitio
Page 39 and 40: 6.2.2 Generation Under development
Page 41 and 42: Under development Table 6-1 List of
Page 43 and 44: Under development TMPM330 (rev0.4)
Page 47 and 48: 6.3.6 Interrupt Service Routine Und
Page 49 and 50: 6.4.2 CG Interrupt Mode Control Reg
Page 51 and 52: 6.4.4 CG Interrupt Mode Control Reg
Page 55 and 56:
6.4.7 NMI Flag Register Under devel
Page 57 and 58:
7 Input/Output Ports 7.1 Port regis
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Under development Port A input enab
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7.1.3 Port C (PC0~PC3) Under develo
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7.1.5 Port E (PE0~PE6) Under develo
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7.1.6 Port F (PF0~PF7) Under develo
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7.1.7 Port G (PG0~PG7) Under develo
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7.1.8 Port H (PH0~PH7) Under develo
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7.1.10 Port J (PJ0~PJ7) Under devel
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Under development Port K input enab
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8.2 Differences in the Specificatio
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Configuration Under development TMP
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Registers 8.2.1 TMRB registers Spec
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Under development 8.2.1.1 TMRBn ena
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Under development 8.2.1.3 TMRB cont
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Under development 8.2.1.5 TMRB flip
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TBnIM (0x4001_0xx8) Under developme
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Under development 8.2.1.9 TMRB time
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Under development 8.3 Description o
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Under development TMPM330 (rev 0.4)
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Page 97 and 98:
• Register setting Under developm
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Under development 8.4 Description o
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Under development The block diagram
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Under development 8.6 Applications
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Prescaler output clock TB5IN0 pin i
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9 Serial Channel (SIO) 9.1 Features
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• Mode 0 (I/O Interface mode) /LS
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Under development 9.3 Operation of
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Under development (Note 1) The pres
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Under development (Note 1) The pres
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• Example baud rate setting: Unde
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fc [MHz] Under development Table 9-
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Under development I/O interface mo
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• Handshake function Data write t
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9.3.10 Transmit FIFO Buffer Under d
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9.3.12 Parity Control Circuit 9.3.1
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Under development 9.3.17 Configurat
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Under development 9.4 Register Desc
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9.4.4 Mode control register 0 SC0MO
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Under development : This is a statu
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Page 141 and 142:
9.4.10 TX FIFO configuration regist
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9.5 Operation in Each Mode 9.5.1 Mo
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SCLK input mode Under development T
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Receiving data SCLK output mode Rec
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Transmit and receive (full-duplex)
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SCLK input mode Under development T
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9.5.2 Mode 1 (7-bit UART Mode) Unde
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9.5.4 Mode 3 (9-bit UART) Under dev
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10. Serial Bus Interface (SBI) Chan
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10.2 Control Under development TMPM
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SBIxCR0 10.4 Control Registers in t
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Under development Table 10-1 Base C
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SBIxBR0 bit Symbol I2SBI0 Under dev
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10.5 Control in the I 2 C Bus Mode
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Under development 10.5.6 Configurin
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Master A Master B Under development
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Under development 10.6 Data Transfe
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SCL pin Write to SBIxDBR SDA pin I
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Slave mode ( = “0”) Under devel
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10.6.4 Generating the Stop Conditio
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Under development 10.7 Control in t
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SBIxDBR SBIxCR2 Under development S
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10.7.1 Serial Clock SCK pin output
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10.7.2 Transfer Modes Under develop
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SCK pin SIOF SO pin bit 6 Under dev
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SCK pin (output) SO pin SI pin IN
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11.2 Registers 11.2.1 Control Regis
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Under development 11.2.5 Software R
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Under development 11.2.7 Receive Bu
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Under development TMPM330 (rev0.4)1
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Under development 11.2.10 Receive C
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Under development 11.2.11 Transmit
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Under development 11.2.13 Transmit
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Under development 11.2.14 Receive I
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11.3 Operations 11.3.1 Reception 11
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(3) Cycle Error Under development C
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(10) Waveform Error Detection Under
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11.3.1.6 Data Sampling Point Under
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11.3.1.8 Detecting Error Interrupt
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Under development TMPM330 (rev0.4)1
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11.3.2.2 Preconfiguration Under dev
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11.3.2.3 Starting Transmission Unde
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(2) ACK error Under development TMP
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Under development 12 Remote control
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Under development 12.2.2 Remote Con
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(Note) Under development When you c
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Under development 12.2.11 Remote Co
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12.3.1.3 Preparation Under developm
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(3) Settings of Data Bit Determinat
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12.3.1.6 Reception Completion Under
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Under development 12.3.1.8 Receivin
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Remote control signal waveform (inp
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Remote control signal in phase meth
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13.1 Registers Under development Th
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ADMOD1 Under development A/D Mode C
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ADREG2AL ADREG2AH ADREG3BL ADREG3BH
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ADREG6EL ADREG6EL ADREG6EL ADREG6EL
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ADCMP0L ADCMP0H ADCMP1L ADCMP1H Und
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13.4 Description of Operations 13.4
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Page 271 and 272:
Under development 3. Fixed channel
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13.4.5 High-priority Conversion Mod
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Under development 14. Watchdog Time
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14.3 Control Registers Under develo
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14.4 Control Register Under develop
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15.3 Control Register Under develop
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MINR Under development (2) Minute c
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DAYR DATER Under development (4) Da
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YEARR YEARR Under development (8) Y
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15.5 Operational description (1) Re
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3. Disabling the clock Under develo
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(2) 1Hz clock Under development TMP
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16.1 Addresses [1] Port [1/4] ADR
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[1] Port 3/4] ADR Register name AD
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[2] 16-bit timer [1/4] ADR Registe
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[2] 16-bit timer [3/4] ADR Registe
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Under development [3] Serial bus in
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[5] 10-bit A/D converter (A/DC) ADR
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[10] Remote control signal preproce
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Under development JEDEC compliant f
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User Boot Mode Under development (1
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(Step-5) Under development TMPM330
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17.2.3 Single Boot Mode Under devel
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Page 323 and 324:
(1) Configuration for Single Boot M
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(5) Restrictions on internal memori
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Under development Table 17-7 Transf
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Under development Table 17-9 Transf
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(6) Operation of Boot Program Under
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Under development returns to the st
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Under development 3) Show Product I
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Under development 4) Chip Erase com
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5) Acknowledge Responses Under deve
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Point A Point B Point C Point D Und
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Start Are all bytes the same? YES A
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(7) General Boot Program Flowchart
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(2) Basic operation Under developme
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Page 353 and 354:
Page 355 and 356:
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Under development Table 17-17 Secur
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Address Normal comma nds Under deve
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(8) Flowchart Address = Address + 0
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18. ROM protection 18.1 Outline Und
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18.3 Register block. Under developm
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18.4 Writing and erasing 18.4.1 Pro
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TMPM330 - Keil

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