TMPM330 - Keil

PLLSEL
5.3.2.4 PLL Selection Register
Under development
: Specifies use or disuse of the clock multiplied by the PLL.
“X1” is automatically set after reset. Resetting is required when using the PLL.
TMPM330 (rev0.4) 5-7
TMPM330
7 6 5 4 3 2 1 0
Bit symbol - - - - - - - PLLSEL
Read/Write R R/W
After reset 0 0 0 0 0 0 0 0
Function “0” is read. Use of PLL
0: Disuse.
X1 selected
1: Use
15 14 13 12 11 10 9 8
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read.
23 22 21 20 19 18 17 16
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read.
31 30 29 28 27 26 25 24
Bit symbol - - - - - - - -
Read/Write R
After reset 0 0 0 0 0 0 0 0
Function “0” is read.
Clock/ Mode Control